CASL Assembly Language Tutoring

Introduction of CASL assembly language grammar

Learning an assembly language needs to Master 3 key points: CPU programmable register structure, addressing mode and instruction system, pseudo instruction.

1, cometcpu programmable Register cometcpu Word length 16 bits, using the numbering from left to right. Bit0 on the leftmost (highest bit), bit15 on the far right (lowest bit)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

1 16-bit general-purpose registers five:

GR0, GR1, GR2, GR3, GR4

General functions: Various arithmetic logic operations

Special function: In addition to the GR0 can be used as a change address register (location pointer) Xr,gr0 can be seen as accumulators.

GR4 as stack pointer (SP)

2 instruction Counter PC one (16-bit)

The address of the 1th word of the instruction being executed (one instruction is two words), and the address of the next instruction in the PC at the end of the instruction (usually the original instruction address +2).

3 State Register FR One (two-bit)

Operation result	FR0	FR1
Greater than	0	0
Equals	0	1
Less than	1	0

FR0 can be regarded as SF (symbol bit), FR1 as ZF (0-bit)

In addition to the arithmetic logic operation instruction (including the shift instruction), the LEA instruction also affects FR

2. Symbolic instruction and addressing mode

OP GR,ADR[,XR]

OP is the operation code, GR is one of five general-purpose registers GR0~GR4, ADR is a 16-bit address code, XR is one of four variable address registers GR1~GR4, [] means can omit.

1 Direct addressing: When [, XR] omitted, for direct addressing.

2) address addressing: Valid addresses E = ADR + (XR), when ADR = 0 o'clock, for register indirection.

3) Immediate number addressing: CASL does not have immediate number addressing. In the LEA instruction, however, when [, XR] is omitted, it can be transmitted as an immediate number. There is no immediate number operation instruction.

4 Register Addressing: CASL also has no register addressing (for source operands). But the LEA directive when ADR = 0 o'clock, can be used for register addressing (data transfer only).

3. CASL Instruction System

1 Take the number instruction LD: Memory → Register

LD GR,ADR[,XR]

2 Storage instruction ST: Register → Memory

ST GR,ADR[,XR]

3 addition Add, subtract SUB, logical AND and, logical OR OR, logical XOR or EOR directives:

ADD	┐
SUB	│
and	├	GR,ADR[,XR]
OR	│
EOR	┘

Memory OP register → Register

4 Arithmetic comparison CPA:

Two signed numbers are compared, the results are not loopback, only affect the flag bit.

CPA GR,ADR[,XR]