Instruction Set changes 1. Address width and operand width prefix
In 64-Bit mode, the default address width is 64-bit, and the default operand width is 32-bit. The prefix of address width and operand width allows 32-bit and 64-bit data and addresses to be mixed in the instruction sequence. The following table (1-7) shows the width of the directive prefix address that is required in IA-32e mode. Note: In 64-Bit mode, 16-bit addresses are not supported. In the beloved and traditional mode, the address Width Function functions the same as in the IA-32 drive architecture. The following table (1-8) shows a valid combination of the 66h command prefix and the Rex. W prefix to specify the operand width in IA-32e operation mode.
In 64-Bit mode, the default operand width is 32 bits, and the Rex prefix includes 4-bit fields to specify 16 different values. The W-bit field of the Rex prefix is specified as Rex. W. If Rex. W = 1, the prefix indicates that the Operation digit 64 is the operand. Note that the software can still use the H prefix of the operand width to switch to the 16-bit operation width. However, if both the Rex. W and 66h prefixes are used, the priority of Rex. W is higher.
In the case of SSE/sse2/sse3 SIMD commands, the 66 h, f2h and f3h prefixes are used as operation code extensions and are considered as part of the commands. In these cases, the valid Rex. W prefix and the extension prefix of the 66h Code have no relationship with each other. 2. Rex prefix
The REX prefix is the new instruction prefix byte introduced in 64-Bit mode. It does the following:
- Specify new GPRS and SSE registers
- Specify the 64-bit code width
- Specify the extended control register (for system software only)
Not all commands require the Rex prefix. This prefix is only required when the instruction references an extended register or uses 64-bit operands. If this prefix is not needed, it will be ignored.
A command can have only one Rex prefix. Once this prefix is used, it must be placed before the extended prefix of the operating code byte or two bytes. The REX prefix at other locations will be ignored.
Commands with the Rex prefix must still follow the traditional 15-byte instruction Width limit. Describes how the Rex prefix conforms to the byte order of the instruction. 3. New encoding of control and debugging registers
In 64-Bit mode, additional encoding is specified for the Controller memory and debugging register. When the Domain Encoding of the modrm register is a control or debugging register, the Rex. r bit is used to modify these domains. These encodings allow processors to access CR8-CR15 and DR8-DR15.
A control register (cr8) is attached to the 64-Bit mode ). Cr8 becomes the task priority register (TPR ). At the first implementation of IA-32e technology, neither CR9-CR15 nor DR8-DR15 were implemented, and access to them would cause invalid code exceptions (# ud ). 4. New commands
The following new commands are introduced in 64-Bit mode with 64-bit extensions.
- Swapgs command
- Syscall and sysret commands
- Cdqe commands
- Cmpsq command
- Cmpxchg16b command
- Lodsq command
- Movsq command
- Movzx (64-bits) command
- Stosq command
5. Stack pointer
In 64-Bit mode, the stack pointer is 64-bit. The stack size is not controlled by one of the SS segment descriptors in the compatibility mode or traditional mode, nor indicated by the instruction prefix.
For implicit stack reference, the indication of the address size is ignored. Except for the far branch, all commands that implicitly reference RSP are 64-bit operands by default in 64-Bit mode. The affected Commands include push, Pop, pushf, popf, enter, and leave. Using these commands in 64-Bit mode, it is impossible to generate a 32-bit stack value for the pressure stack and rollback stack. If the prefix of the 66h operand is used, the 16-Bit Pressure stack and rollback Stack are supported.
When the register RAX-RSP is used as the operand, the default Operating size of the 64-Bit mode does not require the Rex prefix as the pilot of these instructions. If the formula R8-R15 is used as the operand, Rex is still needed. This is because the prefix is required to access the new extended register. 6. Branch Transfer
The 64-bit extension technology expands two branch mechanisms to adapt to the branch of the 64-bit linear address space. They are:
- Near branch transfer is redefined in 64-Bit mode
- In the 64-bit and compatible modes, the 64-bit call gate descriptor is defined as a remote call.
In 64-Bit mode, all near-branch transfers (call, RET, JCC, jcxz, JMP, and loop) are forced to 64-bit. These commands are updated to provide 64-bit rip values without the Rex prefix. The following near transfer is controlled by the valid operand width:
- Truncation of the width of the instruction pointer
- Size of the rollback pressure or rollback caused by call or ret
- Stack pointer increase or decrease caused by call or ret
- Indirect transfer operand size
In 64-Bit mode, all the preceding operations are forced to be 64-bit regardless of the prefix of the operand (the prefix of the operand size is ignored ). However, the displacement area of the relative transfer is still limited by 32 bits; the size of the near-transfer address is not forced to be 64 bits.
The address size affects the size of rcX in jcxz and loop; they also affect the calculation of memory indirect transfer addresses. Such addresses are 64-bit by default, but they can be converted to 32-Bit Width through the address width prefix.
The software will change the priority with a remote transfer. The traditional IA-32 structure provides the calling portal mechanism to allow software to go from one priority to another, although the calling portal can also be transferred without changing the priority. When the call gate is used, the offset of the direct or indirect selector pointer pointing to a gate Descriptor (the low cost of command weight is ignored) can be obtained from the call gate descriptor. The IA-32e pattern redefines the type value of the 32-bit call gate descriptor to make it a 64-bit call gate Descriptor and extends the 64-bit descriptor so that it can accommodate the 64-bit offset. The 64-Bit mode calls the gate descriptor to allow remote transfer to access any location of a valid linear address space. These call Gates also control the code snippet selector (CS), which allows conversion to privileged levels and default sizes and serves as the result of door conversion.
Generally, 32-bit is specified. The only option that specifies full 64-Bit Absolute rip in 64-Bit mode is indirect branch transfer. For this reason, direct remote branch transfer is deleted from the 64-bit instruction set.
The IA-32e mode extends the semantics of sysenter and sysexit instructions so that they operate in a 64-bit bucket. The IA-32e also introduced two new commands: syscall and sysret, which are only valid in 64-Bit mode. Iv. Storage Organization Address Calculation in 1.64-Bit mode
In the 64-Bit mode (if there is no address size change), the valid address is calculated as 64-bit. A valid address is calculated using a 64-bit base and index register and symbol extension to convert to 64-bit.
In 64-Bit mode, linear addresses are equivalent to valid addresses. This rule is not used in non-0-based transactions using FS and GS segments. In 64-Bit mode, the valid address is added, and the valid address is shortened before the 64-bit base address is added. When the address ing mode is in 64-Bit mode, the base address will never be shortened.
In IA-32e mode, Directive pointers are extended to 64-bit to support 64-bit code offsets. The 64-bit instruction pointer assigns the value to rip in the call. The following table describes the differences between rip, EIP, and IP. In general, replacement and direct 64-Bit mode are not extended to 64-bit. They are still limited to 32-bit and symbol extensions in the calculation of valid addresses. However, the 64-Bit mode provides support for 64-bit replacement and direct form of mov commands.
All 16-bit and 32-bit address calculations in IA-32e mode use 0 extensions to Form 64-bit addresses. Address search is the valid address width reduced to the current mode, just as the address width prefix is specified. The result is that the full 64-bit address width is obtained by using 0 extension. Because of this, the 16-bit and 32-bit applications can only access the 4 GB lower of the 64-bit valid address in compatible mode. Similarly, in 64-Bit mode, a 32-bit address can only access 4 GB lower than the 64-Bit mode valid address. 2. Standard addressing
A standard form of address has an address location of 63 until it is more effective, and the macro structure is set to all 1 or all 0.
The IA-32e Pattern Defines a 64-bit linear address, but less digits are supported when implemented. The first processor with a 64-bit extended IA-32e structure will support 48-bit linear addresses. This means that the standard address must put the 64-digit 63 in place 48 fill in 0 or fill in 1, fill in 0 or fill in 1 to see whether the 47 is 0 or 1.
Although the implementation does not use all the 64-bit of the first line address, they need to check the 64-bit to see if the address is in the standard form. If a linear storage reference is not in the standard format, this implementation will generate an exception. In many cases, a general protection exception (# GP) occurs ). However, a stack error (# SS) is generated when the application is displayed or implicitly used ). Implicit stack reference Commands include the push/pop commands and the instructions that use the RSP/RBP registers as the default stack segment registers. In these cases, a canonical Error # SF. If an instruction uses RSP/RBP as the base register and has a segment beyond which a non-SS segment is given, A general protection error (# GP) is caused. Implicit stack references include all push/pop commands and any use of RSP or RBP as a base register. Regular address checks are completed after the privileged check and before the border check. |
