Comparison of common Nic drivers in embedded systems (cs8900a, RTL8019, dm9000)

1. cs8900a
CS8900 chip is a LAN processing chip produced by Cirrus logic, which is very common in the embedded field. It is encapsulated with 100-pin tqfp, which is integrated with a 10-bit Ram and a 10-bit BASE-T Transceiver filter, and provides eight-bit and 16-bit interfaces. CS8900 is connected to the ARM chip in the 16-Bit mode. After the NIC chip is reset, the default operation mode is I/O connection, and the base address is 300 h. Cs8900a also provides other performance and configuration options. Its uniqueThe packet page structure can automatically adapt to changes in network traffic mode and existing system resources.To improve system efficiency.
There are three modes for data transmission between MCU and cs8900a:I/O mode, memory mode, and DMA mode.This design adopts the default cs8900a I/O mode (most of them adopt simple I/O mode due to power consumption and layout requirements)Because the I/O mode is easy to use. In I/O mode, the packetpage structure is accessed by accessing eight 16-bit registers, which are mapped to 16 consecutive addresses in the 2410 address space. When cs8900a is powered on, the default base address of the Register is 0x300 h.
The circuit connection is as follows:

The IO mode of cs8900a is characterized by the packetpage structure. It is very convenient to configure the internal registers of cs8900a using packetpagepointer and packetpagedata port.

# DefineCs8900_pptr * (volatilecs8900_reg *) (cs8900_base + 0x05 * cs8900_off)

//Definition of packetpagepointer

# DefineCs8900_pdata * (volatile cs8900_reg *) (cs8900_base + 0x06 * cs8900_off)

//Packetpagedata Port
 

Set cs8900a using the following function

 Get_reg (  Int  Regno)  // Read register data in 32-Bit mode  
  {
Cs8900_pptr  =  Regno;  //  Regno is the offset address of the register to be read.  
    Return  (Unsigned  Short  ) Cs8900_pdata;  //  Returns the data of the register to be read.  
 }
  Static     Void  Put_reg (  Int  Regno, unsigned  Short  Val)  //  Write register  
  {
Cs8900_pptr  =  Regno;
Cs8900_pdata  = Val;  //  Write register  
  } 

Cs8900_base is the base address and is related to the hardware connection. The hardware schematic diagram determines that the base address of cs8900a is x191000000 in the address space of S3c2410. In I/O mode, the base address of the internal register of cs8900a is 0x300 h by default, and the address in the address space of S3C2410 is 0x19000300.

 
# DefineCs8900_base 0x19000300
 

After completing the preceding steps, the following driver is very easy to write. Use the NIC to suspend the function example:

VoidEth_halt (Void)
{
/*Disable transmitter/receiver mode*/
Put_reg (pp_linectl,0);//Disable Nic
/*"Shutdown" to show chipid or kernel wouldn't find he CS8900...*/
Get_reg_init_bus (pp_chipid );
}
 

Ii. RTL8019

RTL8019AS is a highly integrated Ethernet controller. To provide a completely out-of-the-box plug-and-play solution, RTL8019AS automatically detects between 10 BaseT transceiver, BNC, and AuI interfaces. In addition, eight IRQ buses and 16 Basic address buses provide a loose environment for large resources.
RTL8019AS supports 16 K, 32 K, and 64 K Bytes Brom and flash interfaces. It still provides the page mode feature, which supports 4 MB Brom in 16 KB memory system space.
In addition, Brom's useless commands are used to release Brom memory space. RTL8019AS is designed on a single chip with 16 K-byte SRAM. Its design not only provides more friendly functions, but also saves SRAM storage resources.
The port I/O base address selected by RTL8019 is 300 h. Its address offset of a total of 32, the address space used for 300h-31fh, the address line SA0-SA4 and the CPU A0-A4 connection, SA8-SA9 connected to high level, the rest of the address line connected to low. Connect the A22 and ngcs3 signals of arm to determine which bank the address maps. If A22 is connected to sa8 and ngcs3 is connected to sa5, the addressing range is 0x8340001f ~ 0x83400000.
The driver features that the access to its registers is almost the same as the access to its memory by the CPU. The Register uses the paging technology, and each page register is cheaper than 00 ~ 1f. This simplifies the hardware connection. In addition, RTL8019 has a Brom interface, which can be connected to non-easy-to-lose memory and can read internal data during reset, which is very convenient.
Because it is similar to agreeing to the addressing, and does not adopt the packetpage structure as cs8900a, it is easier to write the driver, but there is one more page to determine the function:
Register configuration function:

 Static  Unsigned  Char Get_reg (unsigned  Int  Regno)  //  Obtain the register value.  
  {
  Return  (  *  (Unsigned  Char     *  ) Regno );
}
  Static    Void  Put_reg (unsigned  Int  Regno, unsigned  Char  Val)  //  Assign a value to a register  
  {
  *  (  Volatile  Unsigned  Char     * ) Regno  =  Val;
} 

Page switching method:

 
Put_reg (rtl8019_command, rtl8019_page0 );
 

Nic suspension function example:

 
VoidEth_halt (Void)
{
Put_reg (rtl8019_command,0x01);//Suspend Nic
}
 

Iii. dm9000
The dm9000 is a fully integrated and cost-effective single-chip fast Ethernet MAC controller with a general processing interface, a 10/100 M Adaptive PHY and 4 k dword Value SRAM. It aims at 3 of low power consumption and high performance processes. 3 V and 5 V Support tolerance. Dm9000 also provides media-independent interfaces to connect all household telephone line network devices or other receivers that support media-independent interfaces. The dm9000 supports 8-bit, 16-bit, and 32-bit interfaces to access internal memory to support different processors. As its cost decreases and its functions become more and more powerful, it is widely used.
For read/write operations on dm9000, correct addressing of dm9000 first. The aen (address allowed) is the input pin chip selection signal. SA4 ~ Sa9 is the address bus 4 ~ When aen is low and sa9 and sa8 is high, while SA7, sa6, sa5, and SA4 are low, dm9000 is selected. Dm9000 default I/0 base address is 300 h.
The cmd pin is used to set command mode. When CMD is high, select the data port. When CMD is low, select the address port. The data port and address port address code are determined by the following:
Dm9000 address port = high-position chip selection address + 300 h + 0 h
Dm9000 data port = high-position chip selection address + 300 h + 4 h
The high part selection address is provided by ngcs3 of S3C2410, that is, 0x100000000 H.

Driver writing features: A cmd signal is used to control whether to read or write dm9000. The architecture is very simple and easy to understand. It is similar to the packetpage structure of cs8900a.
The driving key is as follows:
Read port and write port macros

# DefineDm9000_outb (D, R) (* (volatile u8 *) r = D)
# DefineDm9000_outw (D, R) (* (volatile 2010*) r = D)
# DefineDm9000_outl (D, R) (* (volatile u32 *) r = D)
# DefineDm9000_inb (R) (* (volatile u8 *) R)
# DefineDm9000_inw (R) (* (volatile 2010*) R)
# DefineDm9000_inl (R) (* (volatile u32 *) R)
 

Register configuration function:

Static  U8
Dm9000_ior (  Int  Reg)  //  Read register value  
  {
Dm9000_outb (Reg, dm9000_io );  //  Similar to cs8900a, write the register index dm9000_io  
    Return  Dm9000_inb (dm9000_data );  // Reading dm9000_data is the value of the Register.  
  }
  Static     Void  
Dm9000_iow (  Int  Reg, u8 value)
{
Dm9000_outb (Reg, dm9000_io );
Dm9000_outb (value, dm9000_data );  //  Assign a value to a register  
  } 

Here, dm9000_io is the base address of dm9000, which is selected from the high chip address + 300 h + 0 h, CMD is connected to A2, so dm9000_data is dm9000_io + 4, that is, the high-position slice address is + 300 h + 4 h.
Pending function example

Void  Eth_halt (  Void  )
{
Dm9000_iow (dm9000_gpr,  0x01  );  /*  Power-down phy  */  
Dm9000_iow (dm9000_imr,  0x80  );  /*  Disable all interrupt  */  
Dm9000_iow (dm9000_rcr, 0x00  );  /*  Disable RX  */  
} 

Summary:It can be seen that the wiring of cs8900a is the most complicated and all the address lines need to be connected. cs8900a supports the memory mode and IO mode. RTL8019 is more powerful than cs8900a and provides Brom interface, which uses registers for unified addressing, simple driver. The wiring is relatively simple as long as several IP address lines; dm9000, the most powerful function, adaptive Ethernet speed (10 m/100 m ). Wiring is most simple as long as one address line + one slice line selection.