Complete assembly instructions with gaze

I. Data Transmission instructions
── ─
They transmit data between the storage and registers, registers, and input and output ports.
1. General Data Transmission commands.
MoV transfer word or byte. For example: mov eax, 11 meaning: eax = 11
Movsx first extends the symbol and then transmits it.
Movzx is not extended before transmission.
Push pushes words into the stack.
Pop pops up the word stack.
Pusha pushes ax, CX, dx, BX, SP, BP, Si, di into the stack in sequence.
Popa pops up the stack of DI, Si, BP, SP, BX, dx, CX, and ax in sequence.
Pushad pushes eax, ECx, EDX, EBX, ESP, EBP, ESI, and EDI to the stack in sequence.
Popad pops up the stacks of EDI, ESI, EBP, ESP, EBX, EDX, ECx, and eax in sequence.
Bswap swap the byte order in 32-bit registers
Xchg exchange word or byte. (at least one operand is a register, segment register cannot be used as the operand)
Cmpxchg is equal to limit and swaps the operands. (The second operand must be the accumulators Al/ax/eax)
Xadd switches and then accumulates (the result is in the first operand)
Xlat byte lookup conversion.
── BX points to the starting point of a 256-byte table, and Al is the index value of the table (0-255, that is
([Bx + Al]-> Al)
2. input and output port transfer commands.
In I/oport input. (Syntax: In accumulators, {port │ DX })
Out I/oport output. (Syntax: out {port │ DX}, accumulators)
The input/output port refers to the timing in the immediate mode, and its range is 0-255; The DX indicates the timing in the register,
The value range is 0-65535.
3. Destination Address Transfer command.
Load Lea to a valid address.
Example: Lea dx, string; Save the offset address to DX.
LDS transfers the target pointer and loads the pointer content into Ds.
For example: lDs Si, string; Save the segment address: Offset address to DS: Si.
Les transfers the target pointer and loads the pointer content into es.
For example, les Di and string; Save the segment address: Offset address to ES: Di.
LFS transfers the target pointer and loads the pointer content into FS.
For example: LFS Di, string; Save the segment address: Offset address to FS: Di.
LGS transfers the target pointer and loads the pointer content into Gs.
For example: LGS Di, string; Save the segment address: Offset address to GS: Di.
The LSS transfers the target pointer and loads the pointer content to the SS.
For example: LSS Di, string; Save the segment address: Offset address to SS: Di.
4. Mark transfer command.
Transmit the lahf flag register and load the flag into ah.
Send the sahf flag register and load the ah content into the flag register.
Pushf marks the inbound stack.
Popf marks the exit of the stack.
Pushd 32-bit flag into the stack.
Popd 32-bit marks the stack.


Ii. arithmetic operation commands
── ─
Add addition.
Addition of ADC incoming bits.
INC plus 1.
ASCII code adjustment for AAA addition.
Decimal adjustment of DAA addition.
Sub subtraction.
SBB with borrow subtraction.
Dec minus 1.
NEC reverse (minus 0 ).
CMP ratio. (two operands are used for subtraction. Only the flag bit is changed and the result is not returned ).
ASCII code adjustment for AAS subtraction.
Decimal adjustment of the DAS subtraction.
Mul unsigned multiplication.
Imul integer multiplication.
The above two results are returned to Ah and Al (byte operation), or Dx and ax (word operation ),
AAM multiplication ASCII code adjustment.
Div unsigned division.
Idiv integer division.
The above two items are returned:
Commercial Al delivery, remainder ah, (byte operation );
Or commodity delivery ax, remainder delivery dx, (word operation ).
ASCII code adjustment for aad division.
CBW byte conversion into words (extend the byte symbols in Al to Ah)
The CWD character is converted to a dual character. (extend the character symbol in ax to DX)
Convert the cwde character to a dual character. (extend the word symbol in ax to eax)
CDQ dual-word extension. (extend the characters in eax to EDX)


Iii. Logic Operation commands
── ─
And and operation.
Or operation.
XOR exclusive or operation.
Not inverse.
Test result. (the operation of the two operands only changes the flag bit and the result is not returned ).
SHL logic shifts left.
Sal arithmetic shifts left. (= SHL)
The SHR logic is shifted to the right.
SAR arithmetic shift right (= SHR)
Rol loop shifts left.
Ror loop shifts right.
RCL shifts left through carry loop.
RCR shifts right through carry loop.
In the preceding eight shift commands, the number of shifts can reach 255.
During one shift, you can directly use the operation code, such as SHL ax, 1.
If one shift is performed, the CL registers the number of shifts.
For example, mov Cl, 04
SHL ax, Cl


Iv. String commands
── ─
DS: Si source string segment register: Source string address change.
ES: di target string segment register: Target string address.
CX repetition counter.
Al/ax scan value.
D sign 0 indicates that Si and Di should be manually incremental during repeated operations; 1 indicates that Si and Di should be manually reduced.
The Z mark is used to control the end of a scan or a half operation.
Movs string transmission.
(Movsb transfer character. movsw transfer word. movsd transfer dual word .)
CMPS string ratio.
(Cmpsb is more than the limit character. cmpsw is more than the limit character .)
SCAs string scan.
Compare the content of Al or ax with the target string, and the comparison result is reflected in the flag.
Lods Mount string.
Add the elements (words or bytes) in the source string to Al or ax one by one.
(Lodsb transfer character. lodsw transfer character. lodsd transfer dual character .)
STOs save string.
Is the lods inverse process.
Rep is repeated when CX/ECx <> 0.
Repe/repz is repeated when ZF = 1 or the ratio is equal, and CX/ECx <> 0.
Repne/repnz is repeated when ZF = 0 or the ratio result is not equal, and CX/ECx <> 0.
Repc repeats when cf = 1 and CX/ECx <> 0.
Repnc repeats when cf = 0 and CX/ECx <> 0.


V. Program transfer instructions
── ─
1> unconditional transfer instruction (long transfer)
JMP unconditional transfer instruction
Call process call
RET/retf process returns.
2> conditional transfer instruction (short transfer,-128 to + 127)
(If and only when (sf xor of) = 1, OP1 <OP2)
If Ja/jnbe is not smaller than or not equal to, it is transferred.
Jae/JNB is greater than or equal to transfer.
JB/jnae is smaller than transfer.
Jbe/JNA is less than or equal to transfer.
In the preceding four examples, the result of the unsigned integer operation (Mark C and Z) is used ).
JG/jnle is greater than transfer.
Jge/JNL is greater than or equal to transfer.
Jl/jnge is smaller than transfer.
Jle/jng is less than or equal to transfer.
The above four results are used to test the result of the signed integer operation (S, O, and Z ).
Je/JZ is equal to transfer.
Transfer when JNE/jnz is not equal.
When JC has a bid, it is transferred.
When JNC is not carried.
Transfer when jno does not overflow.
Transfer when the parity of jnp/JPO is odd.
Transfer when the JNS symbol bit is "0.
Jo overflow transfer.
If the parity of jp/jpe is an even number, it is transferred.
Transfer when the JS symbol bit is "1.
3> cyclic control commands (short transfer)
Loop CX is a non-zero loop.
Loope/loopz CX is not zero and the Mark Z = 1 is a loop.
Loopne/loopnz CX is not zero and the Mark Z is 0.
Jcxz CX is transferred at zero time.
Jecxz ECx is transferred when it is zero.
4> interrupt command
Int interrupt command
Into overflow interrupt
Iret interrupt return
5> processor control commands
The HLT processor is paused until an interruption or reset signal occurs.
When the chip lead test is high, the CPU enters the waiting state.
ESC to external processor.
Lock to block the bus.
NOP null operation.
STC sets the carry flag.
CLC flags.
The CMC carry mark is reversed.
STD indicates the position in the direction.
CLD flags in the clear direction.
STI sets the consent to interrupt.
CLI clearance interrupt consent bit.


Vi. pseudoinstructions
── ─
DW definition (2 bytes ).
Proc definition process.
The endp process ends.
Segment definition segment.
Assume creates block register addressing.
The ends segment ends.
End program ends.


VII. processor control commands:
Mark Processing Command CLC (carry position 0 command)
CMC)
STC (the carry position is 1 Instruction)
CLD (set direction flag to 1)
STD (Direction Flag position 1 command)
CLI (0 command for interrupt flag)
STI (Interrupt mark set 1 command)
Nop (no operation)
Hlt)
Wait (waiting)
ESC (code change)
Lock)