Address: http://blog.csdn.net/yihuiworld/article/details/7533335#comments
How to execute the program:
The CPU first finds the entry address of the program in the memory-Address Bus
(8086 has 20 address buses, each of which can be passed to 0 or 1 at a time,
The 20-bit binary number can represent the number of different numbers 2 ^ 20 = 1048576
1048576 byte/1024 = 1024 KB (Note: 8bit (BIT) = 1 byte (byte) 1024 byte (byte) = 1kb 1 MB = 1024kb = 1024x1024b)
1024kb/1024 = 1 MB
So the addressing range is 2 to the power of 20 bytes = 1 m
)
Therefore, the number of root address bus (bus width) determines the range of CPU memory addressing.
The above can also be understood as: the number of CPU addresses is the power of 2, EX: 32-bit CPU addressing range is the power of 2 32 = 4G
Even if the memory capacity is 8 GB at the moment, the CPU can only use the memory address in the middle 4 GB.
Then, the program is delivered to the corresponding register of the CPU through a certain channel, and then the -- Data Bus is executed.
If the CPU needs to control peripheral devices, add or subtract, or read or write memory, etc.-control the bus
CPU +-/* and other operations on data-calculator
Summary: CPU composition = register + controller + internal BUS (connecting various devices to transmit data between them)
Register Controller
|
-------------------------------------------Internal Bus
|
InspectorCPU Structure Diagram
What is a CPU register:
Registers are divided into general registers, segment registers...
Registers are used to store the data or commands to be executed by the CPU.
For example, the ax general register structure of 8086cpu is as follows:
Physical address representation:
Problem: there are 20 IP addresses on the 8086 motherboard. Therefore, a 20-bit binary data is required for addressing.
But the CPU can only transmit 16 bits of binary data at a time. How can this problem be solved?
Example: how to evolve two three-digit numbers into a four-digit number
Ex: 234 and 23 --> xxxx
234 × 10 + 23 --> xxxx
↑
Base Address offset address --> physical address
The preceding implementation is similar to the following in the CPU:
Actual memory address = base address: Offset address
Actual memory address = base address x 16 (x 16 carry, similar to x 10 carry in 10 hexadecimal format) + offset address
Demo: 1402: 100
1402 H (hexadecimal number 4*4 = 16-bit binary number) x 16 + 0100
14020 h -- base address x 16
+ 0100 h -- offset address
--------------
14120 h -- actual physical address
Is that true in the computer?
Win + r --> cmd: Enter the command line in the widows environment and enter the DEBUG command
[Plain]View plaincopy
- C: \ Documents ents and Settings \ Administrator> debug
The debug tool is a real-mode program debugging tool provided by DOS/widows. It can be used to check bytes anywhere in the memory and modify bytes anywhere.
It can be used to execute a program by command to verify the correctness of the program running,
You can also track the execution process, compare the values before and after a command execution, compare and move the data range in the memory, and read and write files and disk sectors.
Enter the D command to view the register content:
[Plain]View plaincopy
- -D
- 0b5d: 0100 02 00 EB 0e 50 B0 03 B4-FF E8 9e 00 58 EB 03 E8 ...... P...
- 0b5d: 0110 1D 01 58 C3 F9 C3 55 51-26 8A 4f 08 34 00 4C 0b... X... uq &. o.4.l.
- 0b5d: 0120 74 0d 8d 6f 09 E8 19 04-73 08 E8 0e 00 E2 F6 F9 t... o... s .......
- The 0b5d: 0130 EB 06 2E 89 2E 5d 91 F8-59 5d C3 26 80 7E 00 00 ......]... y]...
- 0b5d: 0140 74 03 45 EB F6 45 C3 2e-80 0e 56 91 10 E8 C6 ff t. E... e... V .....
- 0b5d: 0150 72 4A 2E 80 26 56 91 EF-50 2E A1 59 91 2B C6 2E RJ... & V... P... y ..
- 0b5d: 0160 01 06 57 91 58 2E 8B 36-59 91 2E 80 3C 00 75 26... W. X... 6y... <. U &
- 0b5d: 0170 2E 80 7C FF 3A 75 09 2e-c7 06 4A 91 09 00 EB 1f... | .....
You can see that the representation of physical addresses is base address: Offset address ex: 0b5d: 0100.
The base address is stored in the segment register in the CPU, and the offset address is stored in the General Register.
Concept of cpu structure and segment address offset