Custom AXI-IP Core

Purpose:

Customizes an IP core and connects to the arm system through the Axi bus.

 

Environment:

Win7 32bit

Vivado2014.4.1

Xilinx sdk2014.4

Development Board:

Zc702

 

Step 1:

Create a custom HDL module. In this experiment, create a 16-bit calculator and save it as test. V. The Code is as follows:

Module test (

Input [15: 0],

Input [15: 0] B,

Input CLK,

Output Reg [15:0] sum

);

[Email protected] (posedge CLK)

Begin

Sum <= A + B;

End

Endmodule

 

Step 2:

Create an IP core, open vivado, and select new IP Core in tools

 

 

Click Next,

 

Select the new Axi peripherals option,

 

Fill in the information and click Next,

 

Fill in the parameters and use the default one here,

 

Click Finish.

 

A new IP address core project will be opened later.

 

Test. V was not added to the project when you created it, double-click the myip_v1_0_AXI_inst-myip_v1_0_S00_AXI.v

 

 

The above code mainly defines the parameters used. It is also the parameter we set in advance when creating an IP core. The data width is 32 bits and the address width is 4 bits;

 

After the parameter settings, this comment allows you to add the required port, which is not required in this experiment;

 

 

 

 

Let's look at the following program:

 

 

The first input port s_axi_aclk is the clock by default, and s_axi_aresetn is the reset;

S_axi_awaddr is the write address, which is omitted later,

From the annotations, we can see that it is a security-level option. This is the Axi standard and will be discussed later;

Another port s_axi_wdata is the written data;

 

Some ports are not described here. You can directly look at the notes and directly look at the several ports that will be used immediately:

S_axi_araddr is the address of the read IP core, and s_axi_rdata is the read register;

 

Next let's take a look

 

Four slv_reg registers are displayed when you create a new one.

Reg [C_S_AXI_DATA_WIDTH-1: 0] slv_reg4;

Another entry is added:

Wire [C_S_AXI_DATA_WIDTH-1: 0] sumout;

The main purpose is to add the test. V module;

 

These registers are

 

 

These codes show that writing data to the custom IP core will write the data to the defined registers. Of course, you can modify these registers by yourself, this experiment will not be changed;

Which address does the User write data? Here:

 

According to the above definition,

 

Addr_lsb = 2, opt_mem_addr_bits = 1;

That is, if you write the data to the axi_awaddr [] part, the data will be written to the four registers. Similarly, when reading the data, you can simply read the code.

 

The preceding figure shows the Data Registers received by the user to write data and the IP core. The following figure shows the output data of the IP core, that is, the registers read when the user reads the IP Core:

 

In this experiment, we made some changes to slv_reg0 to slv_reg4;

 

Finally, add the sample module in the user logic section.

 

Then

On this page, check whether all the check options on the left have been checked. If no check box is checked, select the option and make some simple confirmation. Finally, pack the IP core and save it as zip.

 

Close the IP Core Project, create a system file, open an example project, and add the new IP core to the project. Of course, you must include the new IP core in the project,

 

 

After you add your own IP address to the project, the address is automatically assigned:

 

 

Then confirm the correctness and generate bitstream.

Wait for a moment, no error is reported, then export hardware, and then launch the SDK,

 

 

After opening the SDK, you need to create a new application,

 

Use the simplest helloworld Project template and modify the code:

# Include<Stdio. h>

# Include"Platform. H"

# Include"Xbasic_types.h"

# Include"Xparameters. H"

# Include"Maid"

 

Xuint32 * baseaddr_p = (xuint32 *) xpar_myip_0_s00_axi_baseaddr;

 

Int main()

{

Init_platform ();

 

Print ("Hello world \ n \ r ");

Print ("my_ip test... \ n \ r ");

// * (Baseaddr_p + 0) = 0x00020003;

Pai_out32 (xpar_myip_0_s00_axi_baseaddr, 0x11111111 );

Pai_out32 (xpar_myip_0_s00_axi_baseaddr + 0x4, 0x2 );

Pai_out32 (xpar_myip_0_s00_axi_baseaddr + 0x8, 0X990 );

Pai_out32 (xpar_myip_0_s00_axi_baseaddr + 0xc, 0x100 );

U32r0, R1, R2, R3;

R0 = maid (xpar_myip_0_s00_axi_baseaddr );

R1 = pai_in32 (xpar_myip_0_s00_axi_baseaddr + 0x4 );

R2 = pai_in32 (xpar_myip_0_s00_axi_baseaddr + 0x8 );

R3 = maid (xpar_myip_0_s00_axi_baseaddr + 0xc );

Performance_printf ("R0 = % 0x R1 = % 0x r2 = % 0xr3 = % 0x \ n \ r", R0, R1, R2, R3 );

Cleanup_platform ();

Return0;

}

 

The added xparameters. h header file contains the system address of the custom IP Address:

 

 

After compilation, download the BIT file to FPGA and run the file.

 

Okay. The experiment is over.

 

Reprinted: http://blog.csdn.net/shushm/article/details/49536845

Category: Xilinx microblaf

Custom AXI-IP core ()