DAC Verilog ad5601

First download the data sheet from the official website. The DAC has serial parallel, ad5601 is serial, (requires a lot of clock along the shift internally converted to parallel in the output).

According to the handbook's timing program,

Focus on the baud rate range of the chip

Take a look at the data transfer of the manuals. Valid bits

Module DAC
(
Input CLK,
Input rst_n_in,
Output Reg SCLK,
Output reg Sync,
Output Reg DIN
);

Generating status
REG[5:0] cnt=0;
[Email protected] (Posedge CLK or Negedge rst_n_in)
Begin
if (!rst_n_in)
cnt<=0;
Else
Begin
if (cnt>=34) cnt<=0;
else cnt<=cnt+1;
End
End

Reg[15:0] data_reg=16 ' h1740;

[Email protected] (Posedge CLK or Negedge rst_n_in)
Begin
if (!rst_n_in) begin sclk=0;sync=1; End
ELSE begin
Case (CNT)
0:begin
Data_reg=16 ' h1740;//display of data, 16 bits of the first two invalid bits, the last 6 bit invalid bit, the middle 8 bits is the data bit
End

1:begin Sclk=1;din=data_reg[15];sync=0;end
2:begin sclk=0;end//

3:begin Sclk=1;din=data_reg[14];end
4:begin sclk=0;end//

5:begin Sclk=1;din=data_reg[13];end
6:begin sclk=0;end//

7:begin Sclk=1;din=data_reg[12];end
8:begin sclk=0;end//

9:begin Sclk=1;din=data_reg[11];end
10:begin sclk=0;end//

11:begin Sclk=1;din=data_reg[10];end
12:begin sclk=0;end//

13:begin Sclk=1;din=data_reg[9];end
14:begin sclk=0;end//

15:begin Sclk=1;din=data_reg[8];end
16:begin sclk<=0;end//

17:begin Sclk=1;din=data_reg[7];sync=0;end
18:begin sclk=0;end//

19:begin Sclk=1;din=data_reg[6];end
20:begin sclk=0;end//

21:begin Sclk=1;din=data_reg[5];end
22:begin sclk=0;end//

23:begin Sclk=1;din=data_reg[4];end
24:begin sclk=0;end//

25:begin Sclk=1;din=data_reg[3];end
26:begin sclk=0;end//

27:begin Sclk=1;din=data_reg[2];end
28:begin sclk=0;end//

29:begin Sclk=1;din=data_reg[1];end
30:begin sclk=0;end//

31:begin Sclk=1;din=data_reg[0];sync=0;end
32:begin sclk=0;end//
33:begin sclk=1; Sync=1;end//

Endcase

End
End
Endmodule

DAC Verilog ad5601