Design and Development of an embedded system on ARM9.

4.3.1

 

The mpll generates the master clock, and the upll Master/Slave USB function clock

Bank6 and bank7 must be in the same size.

 

 

4.3.2 Special Function registers

Special Function registers start from 0x4800 0000

 

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There are two PLL (Phase Locked Loop, phase-locked loop, which is learned at high frequency, which can achieve frequency doubling. The high frequency of S3C2410 is produced by this circuit ). One of them is mpll, and m is the main, which is used to generate three clock signals:Fclk (to provide the clock signal to the CPU core, we call the CPU clock speed of the S3C2410 is 200 MHz, which refers to the clock signal, corresponding, 1/fclk is the CPU clock cycle) hclk (for AHB Bus peripherals to provide clock signals, AHB for advanced high-performance bus), pclk (for APB bus peripherals to provide clock signals, APB for advanced peripherals Bus ).