Design and Implementation of UDP-Based Network Cameras

I. Summary

This blog post combines video collection, compression, bus switching, and UDP data transmission to develop a UDP-Based Network Camera. The following describes the specific development process. For the debugging process of some key issues, see the next blog.

 

Ii. Experimental Platform

Hardware Platform: diy_de2

Software Platform: Quartus II 9.0 + NiO II 9.0 + Visual Studio 2008

 

Iii. Experiment Principles 1. Overall system diagram

 

Figure 1 overall system diagram

2. System Workflow

First, the video capture part is always working and VGA is displayed. When the nioshi sends a video data writing command, switch the bus to the video writing mode, and the video compression part starts to work, compress the video data and write it into the SRAM. When a full frame of the image is written, the system notifies the niosii to read the video data. The niosii enters the interrupt service function in the form of an interruption, switch the bus to the video reading mode, and then read the video in the SRAM. After reading a frame of image, switch the bus to the video writing mode again. At the same time, the video data is transmitted, and the PC side receives and displays the video.

3. Description of each module

(1) video collection

Use the routines analyzed in the blog post "de2_ TV routine description.

(2) Video Compression

In order to verify the feasibility of the Network Camera as soon as possible, this part adopts the lossy compression method, that is, one row is collected, one column is collected, and the rgb555 format is used, the final resolution is reduced to 320*240.

(3) Bus Switching

Because video acquisition is implemented using the OpenGL, and network transmission is implemented using the niosii soft core, in order to link the two, the SRAM is used as the memory of the video cache; when you need to store data, switch the bus to the end of the video write, that is, the end of the Quartus II; when you need to transmit the video data, switch the bus to the end of the video read, that is, the end of the niosii.

(4) Network Transmission

The UDP protocol is used. It is mentioned in the blog article "diy_de2 dm9000a Nic debugging routine series (II) -- dm9000a testing, self-sending and receiving, and UDP implementation", which is completed on the nioshi side, the running memory is SDRAM.

(5) PC display

In this section, Visual Studio 2008 is used as the PC software platform to complete the UDP protocol and display the received video data on the control.

 

Iv. Experiment steps 1. Hardware Platform

The top-level file adopts the schematic format, as shown in figure 2.

 

Figure 2 top-level files

FPGA-based underlying files mainly consist of video collection and VGA display, video compression, bus switching, and network transmission of nioii, the schematic diagram of the network transmission except the network transmission of the niosii is generated by using the System File System system (RTL), and all other components must be manually generated.

For the diy_de2 Development Board, the video collection and VGA display sections use sdram1 as the cache, The niosii section only uses sdram0 as the running memory, and sram0 as the bus switch.

In addition, the following issues need attention:

(1) Phase-Locked Loop

The entire system uses a phase-locked loop. The clock input is 50 MHz, the output is clk0: 100 MHz, the physical clock offset is 2ns, And the SDRAM; clk1: 100 MHz, the Controller clock of the sdram1 on the video capturing end; clk2: 100 MHz, and niosii controller clock; in addition, the PLL uses in zero delay buffer mode (with one more warning) and with no compensation (with priority) both modes are supported.

(2) niosii Processor

The system uses the most high-performance processing tool of niosii/F, and disables the second-level caching function. The initialization vector is set to CFI, and the exception vector is set to sdram0.

(3) Two Pio on the niosii end

One input and one output. The input value is set to interrupt and rising edge detection. The output value is set to 0. The input is the read video signal to the niosii, and the output is the niosii to the external write video signal.

(4) time series constraints are timequest tools used.

2. Part II

Part II provides two main functions: Reading image data cached in SRAM and transmitting it through UDP protocol. Both functions are implemented in the interrupt service function. Some key issuesCodeAs follows:

    
 // Read the cached data 
For (J = 0 ; J < 76800 ; J ++ ){ A [J] = Iord (sram_16bit_512k_0_base, J); B [J] = Iord (sram_16bit_512k_0_base, j)> 8  ;  }  //  Set it to high again and write data to the SRAM IOWR (pio_1_base, 0 , 1  ); //  The first packet of data is all 0, which serves as the start signal of an image.      For (I = 0 ; I < 1 ; I ++ ){  For (K = 42 ; K < 1506 ; K ++ ) {Snd [k] = 0  ;} Transmitpacket (SND,  1510 ); // Send repetitively 1468 bytes of data.  }  //  The next 105 packages of data are valid image data.      For (I = 1 ; I < 106 ; I ++ ){  For (K = 42 ; K < 1506 ; K ++ ){  If (K % 2 ) = 0  ) Snd [k] = A [k/ 2 - 21 + I * 732  ];  Else  SND [k] = B [k/ 2 - 21 + I * 732  ];  // Iowr_altera_avalon_pio_data (led_green_base, SND [k]);  //  Msleep (500 );  } Transmitpacket (SND,  1510 ); //  Send repetitively 1468 bytes of data. }

Note: The network transmission part, whether sent or received, is first transmitted at a low level, and then transmitted at a high level.

Note: In the IP address segment initialized by the system, the de2 and pc ip addresses should be correctly entered and placed in the same network segment.

3. PC end

The PC uses the C # language to Implement UDP transmission protocol and video display. The design interface is as follows.

Figure 3 C # Interface

 

  5. Experiment results

VGA display results and PC-side display results are respectively.

 

Figure 4 VGA display

Figure 5 C # display result