Design Experience of a hardware expert

I. Cost Saving
Symptom 1: It doesn't matter how much resistance is used for these high/low resistors. Select an integer of 5 K.
Comment: The market does not have a 5 K resistance, the closest is 4.99 K (precision 1%), followed by 5.1 K (precision 5% ), the cost is 4 times and 2 times higher than 20% of the precision. The resistance of 20% precision is only 1, 1.5, 2.2, 3.3, 4.7, and 6.8 (including an integer multiple of 10). Similarly, 20% precision capacitors only have the above values, if you select another value, you must use a higher precision, and the cost will be doubled, but it will not bring any benefits.
Symptom 2: What color is selected for the indicator on the panel? I think the blue is special. choose it.
Comments: other colors such as red, green, and yellow, regardless of the size (less than 5MM) encapsulation, have been mature for decades, the price is generally less than 5 cents, the blue is something that was invented in the last year 34 S. The technical maturity and supply stability are poor, but the price is four to five times more expensive. Currently, the blue indicator is used only when it cannot be replaced by its hidden color, such as displaying video signals.
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Symptom 3: This logic works well with the 74xx door circuit, but it is too earthy. use CPLD to make it look more upscale.
Comments: The 74xx door circuit is only a few cents, and the CPLD also takes at least a few dozen (GAL/PAL although only a few dollars, but the company does not recommend to use ). The cost has increased by N times, but it has also added several times to production, documentation, and other work.
Symptom 4: Our system requires such a high level of requirements, including MEM, CPU, FPGA, and other chips.
Comment: In a high-speed system, not every part of the system is working at a high-speed state, and the price of each component increases by a certain level, in addition, it also has a significant negative impact on signal integrity.
Symptom 5: The PCB design requirements of this board are not high. Use a finer line to automatically deploy the board.
Comments: Automatic wiring must occupy a larger PCB Area and generate a pass hole that is multiple times better than manual wiring. in products with large quantities, in addition to commercial factors, the price reduction considerations of PCB manufacturers are the line width and the number of pass holes. They affect the PCB yield rate and the number of bit consumption, respectively, saving the costs of suppliers, the reason for the price reduction is also found.
Symptom 6: as long as the program is stable, the code is longer and the efficiency is low.
Comment: The CPU speed and memory space are bought with money. If you spend several days writing code to improve program efficiency, it is absolutely cost-effective to reduce CPU clock speed and memory capacity. The Design of CPLD/FPGA is similar.
Ii. Low Power Design
Symptom 1: Our system is powered by V, so we don't have to worry about power consumption.
Comments: The low power consumption design is not only for power saving, but also for reducing the cost of Power Supply Modules and heat dissipation systems. The reduction of current also reduces the interference of electromagnetic radiation and thermal noise. As the temperature of the device decreases, the lifetime of the device is extended accordingly (the lifetime of the semiconductor device is reduced by half every 10 degrees of increase in the operating temperature)
Symptom 2: These bus signals are pulled with resistors, so you can feel at ease.
Rating: there are many reasons why signals need to be pulled up and down, but not all of them need to be pulled. Up and down the resistor pulls a simple input signal, and the current is also less than a dozen, but pull a drive signal, the current will reach the level of security, the current system usually uses 32-bit address data, and there may be 244/245 isolated bus and other signals, the power consumption of several Watts is spent on these resistors (do not use the idea of 8 cents a power to deal with these watts of power consumption ).
Symptom 3: How can I/O ports not used by the CPU and FPGA be processed? Leave it empty first.
Comments: If unused I/O ports are left blank, a little bit of interference from the outside may become an input signal for repeated oscillation. the power consumption of MOS devices depends on the number of flipped doors. If you pull it up, each pin will also have a micro-security current, so the best way is to set it to output (of course, the outside cannot be connected to other drivers)
Symptom 4: There are so many remaining FPGA resources to use.
Comments: The power consumption of FGPA is proportional to the number of triggers used and the number of flip operations. Therefore, the power consumption of FPGA of the same type may be 100 times different at different times of different circuits. Minimizing the number of High-Speed Flip triggers is the fundamental way to reduce FPGA power consumption.
Symptom 5: these small chips have low power consumption and do not need to be considered.
Point Comment: it is difficult to determine the power consumption of a chip that is not complex internally. It is mainly determined by the current on the pin. An abt16244 consumes less than 1 mA power if there is no load, however, its indicator is that each foot can drive 60 mA of the load (such as matching dozens of Ohm resistance), that is, the power consumption at full load can reach 60*16 = 960mA, of course, it's just that the power current is so large that all the heat falls into the load.
Symptom 6: There are so many control signals in the memory. I only need to use OE and we signals on this board, so we can select the disk to be grounded. In this way, the data output speed is much faster during read operations.
Comments: The power consumption of most of the memory will be more than 100 times more effective in chip selection (regardless of OE and we) than ineffective chip selection, so we should try to use CS to control the chip, in addition, the width of the selected pulse can be shortened as much as possible when other requirements are met.
Symptom 7: how have these signals been rushed? As long as the matching is good
Point evaluation: except for a few specific signals (such as 100base-t and STMs), all of them have been rushed. As long as they are not very large, they do not always need to be matched, even if they do not have to match the best. The output impedance like TTL is less than 50 ohm, and some are even 20 ohm. If such a large matching resistor is used, the current will be very large and the power consumption will be unacceptable, in addition, the signal amplitude will be too small to be used. In addition, the output impedance of the general signal in the output high voltage and the output low voltage is not the same, and it cannot be completely matched. Therefore, you only need to accept the Signal Matching for TTL, LVDS, and 422.
Symptom 8: reducing power consumption is a task of hardware personnel and has nothing to do with software.
Point Comment: The hardware is just a stage, but it is software. Almost every chip access and every signal flip on the bus are controlled by software, if the software can reduce the number of external memory accesses (use the storage device variable more, use the internal cache more), and respond to the interruption in a timely manner (the interruption is usually effective at a low level and has a pull resistance) and other specific measures to reduce the power consumption of specific boards.
Iii. System Efficiency
Symptom 1: The CPU with a clock speed of 70% MB can only process, and it will be okay if the clock speed is MB.
Comment: The processing capability of the system involves a variety of factors. The bottlenecks in the communication business are generally stored, and the CPU speed is faster, and the external access speed is also futile.
Symptom 2: When the CPU uses a larger cache, it should be faster.
Point Comment: The increase in cache does not necessarily lead to an improvement in system performance. In some cases, disabling the cache is faster than using the cache. The reason is that data transferred to the cache must be reused multiple times to improve system efficiency. Therefore, in the communication system, only the instruction cache is opened. Even if the data cache is opened, it is limited to some buckets, such as the stack part. It also requires that the program design take into account the cache capacity and block size, which involves the length and jump range of the key code loop body. If a loop is just a little larger than the cache, if the loop is repeated again, it will be miserable.
Symptom 3: is the multi-task interrupted or queried? Just interrupt.
Peer Evaluation: the interruption is real-time, but not necessarily fast. If there are a lot of interrupted tasks, this will not be returned, and the system will crash soon. If the number of tasks is large but frequent, the CPU is used for the overhead of inbound and outbound interruptions, and the system efficiency is extremely low. If you use the query method, the efficiency can be greatly improved, however, queries sometimes cannot meet real-time requirements. Therefore, the best way is to query interrupted queries, that is, after an interruption, all accumulated tasks are processed and then exited.
Symptom 4: The Timing Sequence of the memory interface is the default configuration of the manufacturer and does not need to be modified.
Comments: BSP sets the default values for the interfaces of the storage device according to the most conservative parameters. in actual application, it should be reasonably adjusted based on parameters such as bus operating frequency and waiting period. Sometimes it can reduce the frequency to improve efficiency. For example, if the ram access period is 70ns and the bus frequency is 40 MB, set the three-cycle access time, that is, 75ns; if the bus frequency is 50 m, it must be set to 4 cycles, but the actual access time slows down to 80 ns.
Symptom 5: If one CPU cannot be processed, two distributions are used for processing, and the processing capability is doubled.
Comments: for brick-moving, two people should be twice the efficiency of one person; for painting, one more person can only help. When using a few CPUs, you need to have a good understanding of the business before you can determine, try to reduce the cost of coordination between the two CPUs, so that 1 + 1 is as close as 2, do not less than 1.
Symptom 6: The CPU has a DMA module. It must be fast to use it to move data.
Point Comment: The real DMA is to enable the two devices at the same time after the hardware grabs the bus, and read the data here within a period. However, a lot of DMA embedded in the CPU is just a simulation. Before starting each DMA, you need to make a lot of preparation work (set the starting address and length). During transmission, you often read the memory saved in the chip first, then write it out, that is, it takes two clock cycles to move data at a time, which is faster than that of the software (no command is required, no additional work such as loop jump ), however, if only a few bytes are moved at a time, a bunch of preparation work is required, which generally involves function calling, which is not efficient. Therefore, this type of DMA is only applicable to big data blocks.
Iv. Signal Integrity
Symptom 1: All these signals have been simulated, so there is no problem.
Point evaluation: the simulation model cannot be exactly the same as the physical model. There are differences between the physical products processed in different batches, let alone the model. Besides, the actual situation is very different, and simulation is impossible, especially crosstalk. Once upon a time, a single board has only a packet of a specific length, which is prone to packet loss. The final reason is that the value of the length field is 0xff. When this data appears on the bus, it interferes with the adjacent we signal, and thus does not write into RAM. Its data will also interfere with we, but the interference is within the acceptable range. However, when the eight-bit bus is at the same time from the 0-side 1, the nearby signal cannot be mounted. The conclusion is that the simulation results are for reference only and there should be enough surplus.
Symptom 2: The M data bus should calculate the high-frequency signal. As for the clock signal, the frequency is only 8 KB, which is not a problem.
Comment: the value of the data bus is generally sampled by an edge of the control signal or clock signal, as long as the competition for this edge to maintain enough time and retention time, if there is interference beyond this range, it will not have much impact on the overhead (of course, it is best not to exceed the maximum voltage that the chip can withstand ), however, no matter how low the frequency (in fact, the spectrum range is very wide), the edge of the clock signal is the key. It must ensure its monotonicity and the hop time must be within a certain range.
Symptom 3: since it is a digital signal, the steep the edge, the better.
Comment: The steep the edge, the wider the spectrum range, the greater the energy of the high-frequency part; the more frequent the signal is, the easier the radiation (such as microwave stations can be made into mobile phones, long Wave Radio cannot be done in many countries), the more likely it will interfere with other signals, and the worse its transmission quality on the wire, therefore, low-speed chips can be used whenever possible ,.
Symptom 4: To ensure a clean power supply, the de-couple capacitor is more beneficial.
Comments: In general, the more power supply the de-couple capacitor will certainly be more stable, but there are also many unfavorable factors: waste of costs, wiring difficulties, power shock current is too large. The key to de-couple capacitor design is to select the right capacity and put it in the right place. General chip manuals are competing for the de-couple capacitor design reference. It is best to follow the manual.
Symptom 5: Signal Matching is really troublesome. How can it be well matched?
Point evaluation: the general principle is that when the transmission time of the signal on the wire exceeds the hop time, the problem of signal reflection becomes important. Signal reflection is caused by uneven line impedance. The purpose of matching is to make the impedance of the drive end, load end and transmission line closer, but can match well, it is also closely related to the topology of the signal line on the PCB, A branch on the transmission line, a passing hole, a corner, a plug-in, and a change in the distance between different locations and the ground line will change the impedance, these factors will make the reflection waveform very complex and difficult to match. Therefore, high-speed signals only use point-to-point methods to minimize problems such as passing through holes and corners.
V. Reliability Design
Symptom 1: this board has been produced in small batches, and no problems have been found after a long test.
Comment: the hardware design and chip application must comply with relevant specifications, in particular, all the parameters mentioned in the chip Manual (voltage, I/O level range, current, timing, temperature PCB wiring, power quality, etc.) cannot be verified by test alone. The company has had a bitter lesson when there are few products. after selling the products for a year or two, the IC manufacturer has changed a production line and our board won't be changed, the reason is that the chip parameters have changed, but they are not beyond the scope of the manual. If you take the manual as the standard, you are not afraid of any changes. If the parameter is out of the scope of the manual, you can claim for it (if your board can be transferred at this time, then your reliability will be even better ).
Symptom 2: as long as the software is required for this part of the circuit, there will be no problem.
Comments: many electrical features on the hardware are directly controlled by the software, but the software is often unexpected. What operations are unpredictable after the program runs. The designer should ensure that no matter what the software does, the hardware should not be permanently damaged in a short period of time.
Symptom 3: if a user operation error occurs, you cannot blame me.
Comment: it is correct to require users to strictly follow the manual operation, but when users are people, when there is a mistake, it cannot be said that if the wrong key is hit, the machine will crash. If the wrong plug is inserted, the Board will be burned. Therefore, all possible errors must be protected.
Symptom 4: this board is broken because of a problem with the end board, and it is not my responsibility
Comments: there should be sufficient compatibility with various external hardware interfaces. You cannot stop because the signal of the other party is abnormal. If it is abnormal, it should only affect the functions related to it. Other functions should work properly, and should not be completely attacked or even permanently damaged. In addition, once the interface is restored, you should immediately restore to normal.