Detailed description of the CPSR register of ARM9.

Detailed description of the CPSR register of ARM9.

Recently I have been studying embedded underlying system development. When writing startup code, I need to set the SP of each mode. I need to adjust the CPU working mode. Some code is as follows:

.equ DISABLE_IRQ, 0x80.equ DISABLE_FIQ, 0x40.equ SYS_MOD, 0x1f.equ IRQ_MOD, 0x12.equ FIQ_MOD, 0x11.equ SVC_MOD, 0x13.equ ABT_MOD, 0x17.equ UND_MOD, 0x1b
msr cpsr_c,#(DISABLE_IRQ|DISABLE_FIQ|SVC_MOD)ldr sp,=_SVC_STACKmsr cpsr_c,#(DISABLE_IRQ|DISABLE_FIQ|IRQ_MOD)ldr sp,=_IRQ_STACKmsr cpsr_c,#(DISABLE_IRQ|DISABLE_FIQ|FIQ_MOD)ldr sp,=_FIQ_STACKmsr cpsr_c,#(DISABLE_IRQ|DISABLE_FIQ|ABT_MOD)ldr sp,=_ABT_STACKmsr cpsr_c,#(DISABLE_IRQ|DISABLE_FIQ|UND_MOD)ldr sp,=_UND_STACKmsr cpsr_c,#(DISABLE_IRQ|DISABLE_FIQ|SYS_MOD)ldr sp,=_SYS_STACK
Cpsr_c is used in the code. What is the relationship between cpsr_c and CPSR?
Division of R0 ~ In addition to a total of 16 registers in R15, there are also 17th registers CPSR (current Program Status Register), called the current program Status Register. Some of the CPSR are used to identify various States, some BITs are used to identify the current working mode. CPSR has four eight-bit regions: Flag domain (F), State domain (s), extended domain (x), and control domain (c ).
In the ARM processor, only the MSR command can directly set the Status Register CPSR or spsr. The command format is as follows:
MSR {cond} psr_fields, # immed_8r (8-bit instant count)
MSR {cond} psr_fields, RM
Among them, the "SRS" refers to CPSR or spsr.
Fields specifies the transfer region. Fields can be one or more of the following (lowercase letters are required ):

 
 

  
  
C control domain shielding byte (PSR [7... 0])
  
  
X extended domain shielded bytes (PSR [27... 8])
  
  
S status domain shielded byte (PSR [31 .... 28])