Differences and features of PCI, CPCI, and cpcie

PCI, CPCI, cpcie
Differences and features

CPCI bus

• As a local bus of the processor system, the PCI bus is designed to connect external devices, rather than the system bus used as the processor, to connect the cache and primary storage.

• (1) PCI bus space and processor space isolation

• (2)
Scalability
Bridge

• (3)
Dynamic configuration mechanism plug-and-play

• (4)
Bus bandwidth

• (5)
Shared bus Mechanism

• (6)
Interruption Mechanism

 

PXI

• The PXI specification is an extension of the CompactPCI specification.

• In the mechanical Specification of CompactPCI, PXI adds Environmental Performance Testing and active cooling units to simplify system integration and ensure interoperability between products of different vendors.

• Based on the high-speed PCI bus, PXI also supplements the timing and trigger characteristics dedicated to the measurement and automation systems.

• PXI is a robust modular instrument platform. It provides a computer-based high-performance standardized measurement and automation solution.

 

Basic concepts of cpcie

• PCI Express interfaces vary based on bus bit width, including X1, X4, X8, and x16 (X2 mode will be used for internal interfaces instead of Slot Mode ). PCI
Express specifications are connected from one channel to 32 channels, with high scalability.

• A shorter PCI Express card can be inserted into a longer PCI
Express slot. The PCI Express interface supports hot plugging. The PCI Express card supports three types of voltages: + 3.3 V, 3.3vaux, and + 12 V.

• PCI Express interface bits used to replace the AGP Interface
For x16, it will be able to provide 5 Gbit/s of bandwidth, even if there is a loss of coding, but still can provide about 4 Gbit/s of actual bandwidth, far more
2.1 Gbit/s bandwidth of 8 X.

 

Cpcie Bus

• The PCI bus uses a parallel bus structure. All external devices on the same bus share the bus bandwidth, while the PCIe bus uses the High-Speed Differential bus.

• End-to-end connection is adopted, so only two devices can be connected in each PCIe link.

• End-to-end Data Transmission

• Reference clock is required for PCIe slots, with a frequency range of 300ppm MHz ±

 

PCI/CPCI technical disadvantages

1) The parallel bus cannot connect too many devices, the scalability of the bus is poor, and inter-line interference will cause the system to fail to work normally; 2)
When multiple devices are connected, the effective bandwidth of the bus will be greatly reduced and the transmission rate will be slowed down. 3)
To reduce costs and minimize mutual interference, You need to reduce the bus bandwidth, or design the address bus and Data Bus in a reusable manner, which reduces bandwidth utilization.

PCIe/cpcie technical advantages

• 1)
It is a serial bus for point-to-point transmission. Each transmission channel has exclusive bandwidth and does not have to affect the performance of the entire system due to the frequency of a hardware. 2) PCI Express bus supports two-way transmission mode and data sub-channel transmission mode. The data tunnel transmission mode is PCI.
Express bus supports multi-channel connection between x1, x2, X4, X8, X12, x16, and x32. The one-way transmission bandwidth of X1 can reach 250 Mb/s, and the two-way transmission bandwidth can reach 500 Mb/s, this is no longer comparable to common PCI bus. For specific configurations, see table 1.
3) PCI Express bus fully utilizes advanced point-to-point interconnection, exchange-based technology, and packet-based protocol to achieve new bus performance and features. Power management, quality of service (QoS), hot swapping support, data integrity, error handling mechanisms, and other advanced features supported by PCI Express bus.
4) Good inheritance with the PCI bus, can maintain the inheritance and reliability of the software. The key PCI features of the PCI Express bus, such as the application model, storage structure, and software interface, are consistent with those of the traditional PCI bus, however, the parallel PCI bus is replaced by a highly scalable and fully serial bus.
5) The PCI Express bus makes full use of the advanced point-to-point interconnection, reducing the complexity of the system hardware platform design.

 

 

• Increase frequency and efficiency in a serial manner. The key limit is what kind of physical transmission media is used. Currently, copper lines are widely used, and the theoretical transmission limit of copper is 10.
Gbps. This is the answer to the ultimate transmission speed of PCI Express.

• After the speed reaches 10 Gbps, you only need to replace the fiber channel to multiply the performance.

 

 

•PCI-ePinX1

 

• X16 mode additional pin Definition

System Board type1 peripheral Board

Type2 peripheral board hybrid peripheral, bridging Slot Switching peripheral Board

 

• Product Name: 3u cpcie/CPCI hybrid backplane Product Description: 3u
Cpcie/CPCI hybrid backboard with 2 p47 power connectors, 1 cpcie system slot, 3 cpcie
Type 1 peripheral slot, three cpcie type 2 peripheral slots, one cpcie switching slot, one hybrid bridging slot, and four CPCI peripheral slots. Details: supports PICMG compliance with two PCIe links
Cpcpe system slot (slot 1) of exp.0)
1 cpcie x16 type 1 peripheral slot
2)
2 cpcie X4 type 1 peripheral slot
3 ~ 4)
3 cpcie X4 type 2 peripheral slot
5 ~ 7)
1 cpcie switch slot 8)
1 cpcie/CPCI bridging slot (slot 9)
Four 32bit CPCI peripheral slots (slot 10 ~ 13)
Supports two 3u plug-in Power Supplies