Duanxx STM32 learning: stm32 bus AMBA, AHB, APB

Duanxx STM32 learning: stm32 bus AMBA, AHB, APB

A few days ago I looked at the main peripherals and circuit design of STM32. Today I began to look at the program design of STM32.

Here I am using the STM32 library V3.5, so I am too lazy to see what registers

The first problem encountered was the internal bus ahb and APB of STM32. Here I checked some information and recorded it.

AMBAAMBA (Advanced Microprocessor Bus Architecture) is an open SoC Bus standard proposed by ARM. It is now widely used in the core of the server guard.
AMBA defines Multi-Bus System(Multilevel busing system), including the system bus and peripheral bus with a lower level.
AMBA supports 32-bit, 64-bit, 128-Bit Data Bus, 32-bit address bus, and byte and half-word designs.
It defines two types of Bus: Advanced High-performance Bus (AHB), also known as ASB (Advanced System Bus ). APB (Advanced peripheral Bus) Advanced peripheral Bus
AHB and ASB are actually one thing, yes High-speed busIt is mainly responsible for interfaces such as embedded processors, DMA controllers, and Memory.
APB is Low Speed Bus, Mainly responsible for peripheral interfaces
AHB and APB are linked through Bridge



Bus Bridges General Office, each module in A system communicates with each other through the Bus. The function of the Bus is to move data and addresses from device A to Device B,
If device A and Device B Consistency (the original article is under discussion. Here I don't know how to translate it better, and the translation is consistent for the time being)Then, device A and Device B can be directly mounted on the same bus and directly interpret the data on the bus.
However, if device A and Device B are inconsistent, then device A and device B must be mounted on two different bus. "Translation", Put the data and address on the bus on device Convert to a format that device B can parseAnd put it on the Bus of Device B. The "Translation" is "Bus Bridge ",
The figure below illustrates the role of Bus Bridge between AHB and APB. The data transmission speed of AHB-connected devices is much faster than that of APB devices. That is to say, the role of this Bus Beidge here is" Buffer thick ky "http://www.bkjia.com/kf/ware/vc/" target = "_ blank" class = "keylink"> memory + k8L2gyPgo8aW1nIHNyYz0 = "http://www.2cto.com/uploadfile/Collfiles/20141027/20141027091626117.png" alt = "\">

We can see that AHB is mainly linked to the kernel and storage management of the system, and APB is mainly distributed to peripherals.


The figure below makes it easier to see the role of AHB and APB: AHB links the system bus, RAM, and so on. apb links Common peripherals: GPIO, UART, etc.








Bus Structure on STM32
First, let's take a look at the bus structure of the F103 series chips.



Note thatTwo APB instancesThey are linked to different peripherals, so there will be definitions of APB1 and APB2 in the library file of STM32:

/** @defgroup APB2_peripheral   * @{  */#define RCC_APB2Periph_AFIO              ((uint32_t)0x00000001)#define RCC_APB2Periph_GPIOA             ((uint32_t)0x00000004)#define RCC_APB2Periph_GPIOB             ((uint32_t)0x00000008)#define RCC_APB2Periph_GPIOC             ((uint32_t)0x00000010)#define RCC_APB2Periph_GPIOD             ((uint32_t)0x00000020)#define RCC_APB2Periph_GPIOE             ((uint32_t)0x00000040)#define RCC_APB2Periph_GPIOF             ((uint32_t)0x00000080)#define RCC_APB2Periph_GPIOG             ((uint32_t)0x00000100)#define RCC_APB2Periph_ADC1              ((uint32_t)0x00000200)#define RCC_APB2Periph_ADC2              ((uint32_t)0x00000400)#define RCC_APB2Periph_TIM1              ((uint32_t)0x00000800)#define RCC_APB2Periph_SPI1              ((uint32_t)0x00001000)#define RCC_APB2Periph_TIM8              ((uint32_t)0x00002000)#define RCC_APB2Periph_USART1            ((uint32_t)0x00004000)#define RCC_APB2Periph_ADC3              ((uint32_t)0x00008000)#define RCC_APB2Periph_TIM15             ((uint32_t)0x00010000)#define RCC_APB2Periph_TIM16             ((uint32_t)0x00020000)#define RCC_APB2Periph_TIM17             ((uint32_t)0x00040000)#define RCC_APB2Periph_TIM9              ((uint32_t)0x00080000)#define RCC_APB2Periph_TIM10             ((uint32_t)0x00100000)#define RCC_APB2Periph_TIM11             ((uint32_t)0x00200000)#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFC00002) == 0x00) && ((PERIPH) != 0x00))/**  * @}  */ /** @defgroup APB1_peripheral   * @{  */#define RCC_APB1Periph_TIM2              ((uint32_t)0x00000001)#define RCC_APB1Periph_TIM3              ((uint32_t)0x00000002)#define RCC_APB1Periph_TIM4              ((uint32_t)0x00000004)#define RCC_APB1Periph_TIM5              ((uint32_t)0x00000008)#define RCC_APB1Periph_TIM6              ((uint32_t)0x00000010)#define RCC_APB1Periph_TIM7              ((uint32_t)0x00000020)#define RCC_APB1Periph_TIM12             ((uint32_t)0x00000040)#define RCC_APB1Periph_TIM13             ((uint32_t)0x00000080)#define RCC_APB1Periph_TIM14             ((uint32_t)0x00000100)#define RCC_APB1Periph_WWDG              ((uint32_t)0x00000800)#define RCC_APB1Periph_SPI2              ((uint32_t)0x00004000)#define RCC_APB1Periph_SPI3              ((uint32_t)0x00008000)#define RCC_APB1Periph_USART2            ((uint32_t)0x00020000)#define RCC_APB1Periph_USART3            ((uint32_t)0x00040000)#define RCC_APB1Periph_UART4             ((uint32_t)0x00080000)#define RCC_APB1Periph_UART5             ((uint32_t)0x00100000)#define RCC_APB1Periph_I2C1              ((uint32_t)0x00200000)#define RCC_APB1Periph_I2C2              ((uint32_t)0x00400000)#define RCC_APB1Periph_USB               ((uint32_t)0x00800000)#define RCC_APB1Periph_CAN1              ((uint32_t)0x02000000)#define RCC_APB1Periph_CAN2              ((uint32_t)0x04000000)#define RCC_APB1Periph_BKP               ((uint32_t)0x08000000)#define RCC_APB1Periph_PWR               ((uint32_t)0x10000000)#define RCC_APB1Periph_DAC               ((uint32_t)0x20000000)#define RCC_APB1Periph_CEC               ((uint32_t)0x40000000) #define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x81013600) == 0x00) && ((PERIPH) != 0x00))/**  * @}  */

The APB speed is described below:

APB1 is limited to 36 MHz, and APB2 can reach 72 MHz at full speed.




Below are the bus architectures of F105 and F107:








Address ing between APB1 and APB2 on STM32