Ecc/EDC Algorithm

Theory:

4-byte error code EDC:

In the CD-ROM sector, there is a 4-byte 32-bit EDC domain, which is used to store the CRC code.

The CRC verification code of the CD-ROM generates a polynomial of 32th order, p (x) = (x16 + x15 + X2 + 1) (x16 + X2 + x + 1 ).

The data block used to calculate the CRC code is the Data byte from the beginning of the slice to the end of the user data zone. Take mode1 as an example,

That is, a total of 2064 bytes are between 0 and. Add 4 bytes of data to 0, and then divide the polynomial, and the remainder is the verification code.

The order of CRC codes stored in EDC is as follows:

EDC:	X24-x31	X16-x23	X8-x15	X0-x7
Byte Number:	2064	2065	2066	2067

　

276-byte error code ECC:

The data, address, verification code and so on in the CD-ROM can be considered to belong to the element or symbol in GF (2 m) = GF (28.

GF (28) indicates that the domain contains 256 elements. The 254 elements except are generated by the Primitive Polynomial p (x.

The CD-ROM used to construct the GF (28) domain p (x) is: p (x) = X8 + X4 + X3 + X2 + 1.

The original element in the GF (28) field is alpha = (0 0 0 0 0 1 0 ).

According to ISO/iec10149, ECC codes in CD-ROM sectors use RSPC codes in GF (28) domains to generate 172 bytes

The P verification symbol and the Q verification symbol of 104 bytes. In each slice, #12 bytes to #2075 bytes and ECC domain

#2076 bytes to #2351 bytes a total of 2340 bytes constitute 1170 words (word ). Each word S (n) is composed of two bytes B,

One is MSB, and the other is LSB. The Nth character is composed of the following bytes,

S (n) = MSB [B (2N+ 13)] + LSB [B (2N+ 12)], where n is 0, 1, 2 ,..., 1169.

Data blocks consisting of 2075 bytes starting from #12 bytes to #2064 bytes are arranged in a 24 × 43 matrix, as shown below:

								NP
		0	1	2	3			41	42
	0	000	0001	0002	...	...	...	0041	0042
	1	0043	0044	0045	...	...	...	0084	0085	Header
	2	0086	0087	0088	...	...	...	0127	0128	+
		P				Q				User Data
										+
MP	22	0946	0947	0948	...	...	...	0987	0988	Some auxiliary data
	23	0989	0990	0991	...	...	...	1030	1031
	24	1032	1033	1034				1073	1074	P-Verification
	25	1075	1076	1077	...	...	...	1116	1117
	26	1118	1119	1120	...	1143				Q-Verification
	27	1144	1145	1146	...	1169
		0	1	2	...	25				(ISO/iec1049)

The element in the matrix is a word. This matrix should be considered as two independent matrices for better understanding and analysis,

One is a 24 × 43 matrix composed of MSB bytes, and the other is a 24 × 43 matrix composed of LSB bytes.

(1) P verification symbols are generated using the () RS code

Each column in 43 columns is represented by a vector and recordedVP. Each column contains 24 bytes of data plus two bytes of p-check bytes, which are represented in the following formula:

Vp =	S (43*0 + NP)
	S (43*1 + NP)
	S (43*2 + NP)
	S (....)
	S (43 * MP + NP)
	S (....)
	S (43*22 + NP)
	S (43*23 + NP)
	S (43*24 + NP)
	S (43*25 + NP)

Where: Np =, 2 ,......, 42; MP = 0, 1, 2 ,......, 25

S (43*24 + NP) and S (43*25 + NP) are P verification bytes. Calculated for this column, the two P verification bytes are called the P verification symbol.

Two P verification bytes are added to the corresponding columns of 24 rows and 25 rows, which forms a 26 × 43 matrix and satisfies the equation.HP×VP= 0.

WhereHPCheck matrix is

HP=	1	1	......	1	1	1
	A25	A24	......	A2	A1	1

(2) q verification symbols are generated using () RS code

After adding the P check byte, a 26 × 43 matrix is obtained. The matrix is rearranged by diagonal elements to obtain a new matrix:

									MQ
		0	1	2			40	41	42	Q0	Q1
	0	0000	0044	0088	...	...	0642	0686	0730	1118	1144
	1	0043	0087	0131	...	...	0685	0729	0773	1119	1145
	2	0086	0130	0147	...	...	0728	0772	0816	1120	1146
	3	0129	0137	0217	...	...	0771	0815	0859	1121	1147
	4	0172	0216	0260	...	...	0814	0858	0902	1122	1148
	22	0946	0990	1034	...	...	0470	0514	0558	1140	1166
NQ	23	0989	1033	1077	...	...	0513	0557	0601	1141	1167
	24	1032	1076	0002	...	...	0556	0600	0644	1142	1168
	25	1075	0001	0045	...	...	0599	0643	0687	1143	1169

 

A vector consisting of 43 MSB bytes and LSB bytes on each diagonal line is recordedVQ.VQChange the line vector in the 26 × 43 matrix.

On line NQVQThe vector contains the following Bytes:

VQ =	S (44*0 + 43 * NQ)
	S (44*1 + 43 * NQ)
	S (44*2 + 43 * NQ)
	S (....)
	S (44 * MQ + 43 * NQ)
	S (....)
	S (44*41 + 43 * NQ)
	S (44*42 + 43 * NQ)
	S (43*26 + NQ)
	S (44*26 + NQ)

Where: NQ = 0, 1, 2 ,..., 25; MQ = 0, 1, 2 ,..., 42

S (43*26 + NQ) and S (44*26 + NQ) are Q validation bytes.VQIn (44 *MQ+ 43 *NQ) The result of the byte number operation is MoD (1118.

Put the two Q verification bytes generated by the () RS code into the correspondingVQThe end of the vector and satisfies the following equation:HQ×VQ= 0

WhereHQCheck matrix is

HQ=	1	1	......	1	1	1
	A44	A43	......	A2	A1	1

() RS code and () RS code can correct an error that occurs on any row and any column, and can be quite reliable

Detects multiple errors in travel and columns. If multiple errors occur in an array, reference technology provides

An algorithm called layered ECC that can cancel multiple errors. Its core idea is to execute row correction and column correction in turn.

The ECC algorithm first calculates the principals of each row in the MSB matrix and the LSB matrix.SrI (I= 0, 1 ,..., 25) and correction of each column

ChildSCJ(J= 0, 1 ,..., 44 ). Because (45, 43) RS code is usedSRIAnd everySCJBoth have two school principals.

IfSRI= 0, indicatesIThe row has no errors, such as S.CJ= 0, indicatingJNo errors.

The ECC algorithm first corrects the rows with only one error. After these errors are canceled, only one column is corrected. After a row-and-column transaction

After correction, only a few errors are left. After performing an alternate row-column error correction, all errors can be eliminated.

The RS code correction algorithm contains the error location and error value, and the error location is determined by the school administrator.Sr (I-K),SRI,Sr (I + M)

AndSCJ,SC (J + l)OK, so only the problem of incorrect value is left. This problem has been solved when we discuss the RS code.

For the data in the CD-ROM memory, after the CIRC correction, the bit error rate in bytes can be smaller than 10-9, and then after the RSPC error correction,

The byte error rate can be less than 10-13, which satisfies the requirements of the computer for the bit error rate smaller than 10-12.

The calculation range of mode1 EDC is 2063 bytes from #0 bytes to #2064 bytes.

For mode2 form1 EDC, the calculation range is from #16 bytes to #2071 bytes, a total of 2056 bytes.

For mode2 form2 EDC, the calculation range is 2347th bytes from #16 bytes to 2332 bytes.

ECC calculates 2075 bytes from #12 bytes to #2064 bytes.

Program:

/* LUTs used for computing ECC/EDC */static BYTE ecc_f_lut[256];static BYTE ecc_b_lut[256];static DWORD edc_lut[256];/* Init routine */static void eccedc_init(void){DWORD i, j, edc;for(i = 0; i < 256; i++){j = (i << 1) ^ (i & 0x80 ? 0x11D : 0);ecc_f_lut[i] = j;ecc_b_lut[i ^ j] = i;edc = i;for(j = 0; j < 8; j++) edc = (edc >> 1) ^ (edc & 1 ? 0xD8018001 : 0);edc_lut[i] = edc;}}/***************************************************************************/// Compute EDC for a blockvoid edc_computeblock( const BYTE *src, WORD size, DWORD *dest ){DWORD edc=0x00000000;while(size--) edc = (edc >> 8) ^ edc_lut[(edc ^ (*src++)) & 0xFF];dest[0] = (edc >>  0) & 0xFF;dest[1] = (edc >>  8) & 0xFF;dest[2] = (edc >> 16) & 0xFF;dest[3] = (edc >> 24) & 0xFF;}/***************************************************************************/// Compute ECC for a block (can do either P or Q)static void ecc_computeblock( BYTE *src, DWORD major_count, DWORD minor_count, DWORD major_mult, DWORD minor_inc, BYTE *dest){DWORD size = major_count * minor_count;DWORD major, minor;for(major = 0; major < major_count; major++){DWORD index = (major >> 1) * major_mult + (major & 1);BYTE ecc_a = 0;BYTE ecc_b = 0;for(minor = 0; minor < minor_count; minor++){BYTE temp = src[index];index += minor_inc;if(index >= size) index -= size;ecc_a ^= temp;ecc_b ^= temp;ecc_a = ecc_f_lut[ecc_a];}ecc_a = ecc_b_lut[ecc_f_lut[ecc_a] ^ ecc_b];dest[major              ] = ecc_a;dest[major + major_count] = ecc_a ^ ecc_b;}}// Generate ECC P and Q codes for a blockstatic void ecc_generate( BYTE *sector, int zeroaddress){BYTE address[4], i;/* Save the address and zero it out */if(zeroaddress) for(i = 0; i < 4; i++){address[i] = sector[12 + i];sector[12 + i] = 0;}/* Compute ECC P code */ecc_computeblock(sector + 0xC, 86, 24,  2, 86, sector + 0x81C);/* Compute ECC Q code */ecc_computeblock(sector + 0xC, 52, 43, 86, 88, sector + 0x8C8);/* Restore the address */if(zeroaddress) for(i = 0; i < 4; i++) sector[12 + i] = address[i];}/***************************************************************************/// Generate ECC/EDC information for a sector (must be 2352 = 0x930 bytes), Returns 0 on successvoid eccedc_generate(BYTE *sector, int type){DWORD i;switch(type) {case 1: /* Mode 1 */edc_computeblock(sector + 0x00, 0x810, sector + 0x810);/* Write out zero bytes */for(i = 0; i < 8; i++) sector[0x814 + i] = 0;ecc_generate(sector, 0);break;case 2: /* Mode 2 form 1 */edc_computeblock(sector + 0x10, 0x808, sector + 0x818);ecc_generate(sector, 1);break;case 3: /* Mode 2 form 2 */edc_computeblock(sector + 0x10, 0x91C, sector + 0x92C);break;  }}