Embedded Learning-uboot-lesson6-Clock initialization

1 6410 Clock System

From the schematic you can know the following:
1. Using 12M crystal Oscillator
2 has three dividers APLL MPLL EPLL
3. Generated four clocks aclk hclk PCLK SCLK
Here are the range of applications for several clocks:

Which aclk for the system clock, HCLK and PCLK for various peripherals and internal clocks, SCLK for the time being not considered

2: initialization Process

As can be seen, the SYSCLK is the system clock, the initial frequency is 12MHZ, when the frequency is set, the system frequency for a period of time is 0, this time is lock times, if you want to set up, you can operate, but generally do not need, keep the default.

To set the clock, you need to take a few steps:
1 Setting Lock Time
2. Set the Divide factor
3. Set the CPU-to-asynchronous mode of operation
4. Set the APLL.MPLL output frequency

• 1 Setting Lock Time

Default is the initial value, so do not need to do

For example, 6410 a total of three locktime are Apll_lock mpll_lock epll_lock, the default value of the register is 0XFFFF, so remain unchanged, do not need to change

• 2. Set the Divide factor

The main is to set the proportional relationship between ACLK hclk PCLK SCLK or to set the frequency range between them.

Can simplify the generation process of frequency

Where the red part is the frequency required for this lesson clock, it is based on the frequency of 6410 in Uboot, so you need to set the parameters according to the frequency set.

Look at the above two pictures, you can learn that to set the frequency of ARMCLK HCLKX2 hclk PCLK, you need to set
Divarm DIVhclkx2 divhclk divpclk value,

Depending on the red number, you can determine the value of four numbers
1.armclk=533/(ratio+1) =533 so arm_ratio=0
namely Divarm=0
2.hclkx2=533/(hclkx2_ratio+1) =266 for Hclkx2_ratio=1
namely Divhclkx2=1
3.hclk=hclkx2/(hclk_ratio+1) =133 so hclk_ratio=1
namely Divhclk=1
4.pclk=hclkx2/(pclk_ratio+1) =66 so pclk_ratio=3
namely Divpclk=3
That

#define CLK_DIV0 0x7e00f020#define DIV_VAL ((0X0<<0)|(0X1<<9)|(0X1<<8)|(0X3<<12))  @        r0,=CLK_DIV0 @设置分频系数        r1,=DIV_VAL  @将DIV_VAL的值写入寄存器        r1,[r0]

• 3. Set the CPU-to-asynchronous mode of operation

When the CPU clock is not the same as that of the memory, the clock mode of the CPU needs to be set to asynchronous mode

According to this, the 7th bit needs to be set to 0 asynchronous operation mode, and the 6th bit must be set to 0, the main reason is to make HCLKx2 get the clock source from MPLL instead of APLL, as shown in.

        #define OTHERS 0x7e00f900        r0,=OTHERS @设置异步工作模式 第7位为0 第6位为0(时钟选择器)        r1,[r0]        r1,r1,#0xc0   @        r1,[r0]

• 4. Set the APLL.MPLL output frequency

To set the value of APLL and MPLL to 533Mhz, based on the calculation formula and the given table, it is necessary to set the mdiv=266 pdiv=3 sdiv=1
The corresponding register is configured, and the 31st enable bit needs to be set to 1

#define MPLL_CON 0X7E00F010#define APLL_CON 0X7E00F00c#define PLL_VAL ((1<<31)|(266<<16)|(3<<8)|(1<<0))        r0,=APLL_CON @设置为533Mhz        r1,=PLL_VAL        r1,[r0]        r0,=MPLL_CON        r1,=PLL_VAL        r1,[r0]

• 5 Select Clock Source

Depending on whether you need to use a crystal frequency or MPLL as a subsequent clock source, you need to set the Clk_src[1]=1


Configure the Register to 1 according to the two images above

#define CLK_SRC 0x7e00f01c        r0, =CLK_SRC @选择时钟源为APLL MPLL还是外部        movr1#0x3      @APLL MPLL        r1, [r0]                mov pc,lr

The total code:

@**************************** @name: Start. S@by: Stone@time:2016.6. the@function: @ exception Vector table @ Set SVC mode @ off watchdog @ off interrupt @ off mmu@ Peripheral Base Address initialization @ Lit led@ Clock initialization @****************************. Text. Global_start @ Declare _start as a global variable_start:b Reset Ldr pc, _undefined_instruction ldr pc, _software_interrupt ld R pc, _prefetch_abort Ldr pc, _data_abort ldr pc, _not_used LDR PC, _irq Ldr pc, _fiq_undefined_instruction: . WordUndefined_instruction_software_interrupt:    . WordSoftware_interrupt_prefetch_abort:    . WordPrefetch_abort_data_abort:        . WordData_abort_not_used:      . WordNot_used_IRQ:           . WordIrq_fiq:           . WordFiqundefined_instruction:@ Handle undefined instruction exceptionNOPSoftware_interrupt:@ Soft InterruptNOPPrefetch_abort:@ prefetch Instruction exceptionNOPData_abort:@ Data Access exceptionNOPnot_used:@ EmptyNOPIRQ:@ InterruptNOPFiq:@ Fast InterruptNOPReset:@reset BL set_svc @ set to svc mode BL Set_peri_port @ Peripheral Base Address initialization bl Disable_watchdog @ off watchdog BL D Isable_interrupt @ off interrupt bl Disable_mmu @ off MMU bl init_clock @ clock initialization bl light_led @ Light LEDset_svc:MrsR0, CPSR @ takes the value out of the CPSR register BICR0,R0,#0x1f @ 5-bit m[4:0] Clear 0OrrR0,R0,#0xd3 @0b10011 is converted to 16 0x13 and in order to mask IRQ and FIQ, it can be set to 0b11010011 that is 0xd3MSR CPSR,R0@ Send value back to CPSR registermovPC, LR @ backSet_peri_port:LdrR0, =0x70000000@ Base Address OrrR0,R0,#0x13 @256mbMCR P15,0,R0, C15,C2,4@ Write CP15movPC, LR#define PWTCON 0x7e004000 @WTCON RegisterDisable_watchdog:LdrR0, =pwtcon @ Load the address intoR0        mov R1,#0x0 @ 0, turn off the watchdogStrR1,[R0]movPc,lrDisable_interrupt:MvnR1,#0x0 @0x0, give R1LdrR0,=0x71200014@VIC0 StrR1,[R0] LdrR0,=0x71300014@VIC1 StrR1,[R0]movPc,lrDisable_mmu:MCR P15,0,R0, C7,c7,0@ Make Icache and Dcache invalid MRC P15,0,R0, C1,C0,0@read Control Register BICR0,R0,#0x00000007 @mmu and Dcache 0MCR P15,0,R0, C1,C0,0@write Control RegistermovPc,lr#define CLK_DIV0 0x7e00f020#define CLK_SRC 0x7e00f01c#define OTHERS 0x7e00f900#define MPLL_CON 0x7e00f010#define APLL_CON 0x7e00f00c#define PLL_VAL ((1<<31) | ( 266<<16) | (3<<8) | (1<<0))#define DIV_VAL ((0x0<<0) | ( 0X1<<9) | (0x1<<8) | (0x3<<12))Init_clock:LdrR0, =clk_div0 @ set divide coefficient ldrR1, =div_val strR1,[R0] LdrR0, =others @ Set asynchronous mode of operation7Bit is0The6Bit is0(clock selector) LDRR1,[R0] BicR1,R1,#0xc0StrR1,[R0] LdrR0, the =apll_con @APLL set to533Mhz LDRR1, =pll_val strR1,[R0] LdrR0, the =mpll_con @MPLL set to533Mhz LDRR1, =pll_val strR1,[R0] LdrR0, =CLK_SRC @ Select whether the clock source is APLL MPLL or externalmov R1,#0x3 @APLL MPLLStrR1, [R0]movPc,lr#define GPMCON 0x7f008820 @ Control Register#define GPMDAT 0x7f008824 @ data Registerlight_led:LdrR0, =gpmcon LDRR1,=0x1111@ Output Mode strR1,[R0] LdrR0, =gpmdat LDRR1,=0x00@ Low-lit strR1,[R0]movPc,lr

Rookie one, if there is a mistake, a lot of advice ...

Embedded Learning-uboot-lesson6-Clock initialization