Embedded System CORTEX-A8 Processor programming

3rd Chapter CORTEX-A8 Processor Programming

1. Introduction to ARM programming

• In the development of embedded systems, the main programming languages currently used are C and assembler. In many places, such as the initialization of hardware system at boot time, including the setting of CPU state, interrupt enable, the setting of the main frequency, as well as the control parameters and initialization of RAM are used in assembly language. Assembly language is closely related to the instruction set of CPU, which is an indispensable method for the development of embedded system in the lower level.

Arm Embedded System program design and the use of ARM microprocessor resources are closely related. Only by understanding the working mode, state, memory organization, addressing mode of arm microprocessor, and mastering the instruction system of ARM, it is possible to write the applicable arm program.

2. CORTEX-A8 processor mode and status

Processor Mode

Changing the mode of the processor: Software control external interrupt exception handling

User mode: Normal mode, cannot access certain protected system resources, cannot change mode unless an exception occurs

Privileged mode: Free access to system resources and change mode in addition to user mode

System mode: Exception entry is not allowed, same register as user mode, not restricted by user mode

Processor Status

The CORTEX-A8 processor has 3 operating states, which are controlled by the T-bit and J-bit of the CPSR register.

L Arm State: performs 32-bit aligned arm instruction, T-bit and J-bit is 0.

L Thumb State: Performs a 16-bit or 32-bit THUMB2 instruction, and the T-bit is 1,j bit 0.

L Thumbee State: Performs a variant of a 16-bit or 32-bit half-word aligned THUMB2 instruction set designed for dynamic generation of targets. T-bits and J-bits are 1.

The operating state of the processor can be converted between the following states:

L convert between arm state and thumb state

Use BL and BLX instructions and load to PC.

L Convert between thumb State and Thumbee state

Use the Enterx directive and the Leavex directive.

An exception causes the processor to enter the arm state or thumb state. Normally, when exiting exception handling, the processor restores the original T-bit and J-bit values.

3. Cortex-a8 Memory Organization

1 Data Types

CORTEX-A8 supports the following data types:

1) Double word, 64 digits;

2) Word, 32 bits (4 bytes);

3) Half word, 16 bits (takes two bytes);

4) Bytes, 8 bits.

 

2 Storage formats

The CORTEX-A8 processor supports small-endian format and byte invariant. In addition, the processor supports mixed-size-end formats (both big-endian and small-end formats) and non-aligned data access. The read of the instruction is always done in the small-ended format.

the storage organization structure of ARM :

32-bit long address, which sees memory as a linear combination of bytes starting with 0 addresses, that is, an address corresponds to a storage byte , which is scoped to 232 bytes (8-bit binary number).

3 Register Group

The CORTEX-A8 processor has a total of 40 32-bit long registers.

L 33 General purpose registers.

L 7 Status Registers:

--1 a CPSR (current Programs status register, present program status register);

--6 a SPSR (Saved program status register).

These registers cannot be accessed concurrently, and the processor state and operating mode determine which registers are available to the programmer.

L Non-grouped universal register R0-R7

R0--R7 in 16 data registers are non-grouped universal registers that are used to hold data and addresses .

L Packet General register R8-R15, processor mode determines physical register

--r8-r12 Register: Fast Interrupt and other mode two groups;

--r13,r14 Register: Divided into 7 groups, users and management mode shared;

R13: Also known as SP, stack pointer

R14: Also known as LR, link register

--r15: Also known as PC, program counter, all modes are shared;

L Current Status Register CPSR: all modes are shared;

The state of the group holds the register Spsr:6 the exception mode corresponds.

Status Register

Current program Status register CPSR and 6 state Save registers SPSR main functions are as follows:

L Save the information of the most recently executed arithmetic or logical operation;

L control the interruption of the permit or prohibit;

L Set the processor operating mode.

4 Exceptions

exceptions are methods that the system handles external asynchronous events.

After an exception occurs, the processor forces the execution of the program from the fixed memory address corresponding to the exception type, which is called the exception vector table .

Abnormal Entry

(1) Save the address of the next instruction in the corresponding LR register.

(2) Copy the CPSR to the corresponding SPSR.

(3) force the value of CPSR mode bit m[4:0] to the corresponding exception mode value

(4) forcing the PC to remove an instruction from the associated anomaly vector.

(5) The user can set an interrupt stop bit to block or turn on exception nesting. If the processor is in the thumb state when the exception occurs, it automatically switches into the arm state when the PC is loaded with the interrupt vector address.

exit of Exception:

(1) The value of the LR register minus the corresponding offset (the offset is different depending on the exception), sent to the PC.

(2) Copy the SPSR back into the CPSR.

(3) Clear interrupt Disable bit flag.

5 Addressing Mode

Addressing is the way to find real operand addresses based on the address Code field given in the instruction

Register addressing ADD R0,R1,R2; r0=r1+r2

Immediately addressed MOV R0, #0xff00; r0ß0xff00

Register shift addressing ADD R3,R2,R1,LSL #3; r3=r2+8xr1

Register indirect addressing SWP R1,R1,[R2]; R0 and [R1] values are exchanged

Variable addressing STR r1,[r0,#-2]; [R0-2]ßR1

Block copy addressing Stmia R0!,{R1-R7}

Multi-register addressing Ldmia R1,{R0,R2,R5}; r0=[r1],r2=[r1+4],r5=[r1+8]

Because the transmitted data item is always 32-bit words, the base R1 should be aligned with the word.

Relative addressing Destination address = pc Current value + instruction-given designator offset address

Stack addressing STMFD SP!,{R1-R7,LR}; r1-r7,lr into stack, full decrement stack

typical stacks and what they mean

grow Upward , also known as the increment stack, where the address grows in the high address direction.

grow downward , also known as the descending stack, where the address grows in the low address direction.

full Stack , the stack pointer points to a valid data item that is last pressed into the stack.
empty Stack , the stack pointer points to the empty position where the next data item is placed.

 

6. Instruction System

Basic format <opcode> {<cond>} {S} <Rd>, <rn>{,<operand2>}

2nd operand <operand2>--constant expression

8-bit bitmap data, which is a 18-bit constant, is obtained by looping the right-shift even digits

Condition code

Memory Access Instructions

LDR and STR Directive applications

1. Load/store words and unsigned byte directives

LDR R2,[R5]; R5 the word data that points to the address R2

STR r1,[r0, #0x04]; store R1 data to r0+0x04 address

LDRB R3,[R2], #1; deposit byte data R2 to address r3,r2=r2+1

STRB R6,[R7]; R7 byte data that points to the address is stored R6

2. Load/Store Half-word and signed byte directives

LDRSB R1,[R0,R3]; storing byte data on R0+R3 address in R1, high 24-bit with symbol extension

LDRH R6,[R2], #2; R2 the half-character data that points to the address into R6, the high 16 bits are expanded with 0, and after reading, r2=r2+2

STRH r1,[r0, #2]! To save the R1 half-word data to the r0+2 address,

; only modify the low 2 bytes of data, r0=r0+2

Multi-register access stack operation

Data processing instructions (data processing instructions only operate on the contents of the register, not on the in-memory data.) All ARM data processing instructions can optionally use the S suffix and affect the status flag):

Data Transfer Instructions

arithmetic logic operation instruction;

Compare Directives

 

Status Register Directives

READ: The MRS Instruction can read the status register CPSR and SPSR

MRS R1,CPSR; Read the CPSR status register and save it to R1

Write: