[email protected]:~/my03$ lltotal 12-rw-rw-r-- 1 chunli chunli 2703 Apr 13 03:49 head. s-rw-rw-r-- 1 chunli chunli 532 apr 13 03:50 leds.c-rw-rw-r-- 1 chunli chunli 312 apr 13 03:50 makefile[email protected] : ~/my03$ cat head. s @*************************************************************************@ file:head.s@ Function: Set SDRAM, copy the program to SDRAM, then skip to SDRAM to continue execution @******************************************************************* .equ mem_ctl_ base, 0x48000000.equ Sdram_base, 0x30000000.text.global _start_start: bl disable_watch_dog @ turn off watchdog, otherwise the CPU will continue to restart bl memsetup @ set up storage controllers bl copy_steppingstone_to_sdram @ copy code to SDRAM ldr pc, =on_sdram @ jump into SDRAM to continue execution of ON_SDRAM:&NBSP;&NBSP;&NBSP;&NBSP;LDR&NBSP;SP, =0x34000000 @ Set up Stacks bl mainhalt_loop: b halt_loopdisable_watch_dog: @ Write 0 to watchdog Register Mov r1, #0x53000000 mov r2, #0x0 str r2, [r1] mov pc, lr @ Back to copy_steppingstone_to_sdram: @ Copy all Steppingstone 4K data to SDRAM @ steppingstone start address is 0x00000000, SDRAM start address is 0x30000000 mov r1, #0 ldr r2, =SDRAM_BASE mov r3, #4 *10241: &NBSP;&NBSP;LDR&NBSP;R4,&NBSP;[R1], #4 @ read 4 bytes of data from Steppingstone and let the source address add 4 &NBSP;&NBSP;&NBSP;STR&NBSP;R4,&NBSP;[R2], #4 @ copy this 4-byte data into the SDRAM and let the address of the target add 4 cmp r1, r3 @ Decide whether to complete: the source address is equal to Steppingstone's address? bne 1b @ if not finished, continue mov pc, lr @ return memsetup: @ set up the storage controller to use peripherals such as SDRAM mov r1, #MEM_CTL_BASE @ Start address of the 13 registers of the storage controller adrl r2, mem_cfg_val @ The starting storage address for these 13 values add r3, r1, #52 @ 13*4 = 541: ldr r4, [r2], #4 @ Read the set value and let R2 add 4 str r4, [r1], #4 @ write this value to the register and let R1 add 4 cmp r1, r3 @ Determine if all 13 registers are set bne 1b @ if not written, Continue mov pc, lr @ return. Align 4mem_cfg_val: @ Storage Controller 13 register setting values .long 0x22011110 @ BWSCON .long 0x00000700 @ bankcon0 .long 0x00000700 @ bankcon1 .long 0x00000700 @ bankcon2 .long 0x00000700 @ bankcon3 .long 0x00000700 @ BANKCON4 .long 0x00000700 @ BANKCON5 .long 0x00018005 @ BANKCON6 .long 0x00018005 @ BANKCON7 .long 0x008C07A3 @ REFRESH .long 0x000000B1 @ banksize .long 0x00000030 @ mrsrb6 .long 0x00000030 @ MRSRB7[email protected]:~/my03$ [email protected]:~/my03$ [email protected]:~/my03$ [email protected]:~/my03$ [email protected]:~/my03$ [email protected]:~/my03$ [email protected]:~/my03$ [email protected]:~/my03$ cat leds.c #defineGPFCON (* (volatile unsigned long *) (0x56000050) #defineGPFDAT (* (volatile unsigned long *) 0x56000054) #defineGPF4_out (1<< (4*2)) #defineGPF5_out (1<< (5*2)) #defineGPF6_out (1<< (6*2)) void Wait (volatile unsigned long dly) {for (; dly > 0; dly--);} Int main (void) {unsigned long i = 0; Gpfcon = gpf4_out| Gpf5_out| gpf6_out;// set led1,2,4 corresponding GPF4/5/6 three pins to output while (1) {WAIT (30000); gpfdat = (~ (i<<4)); // light led1,2,4if (++i == 8) i = 0 according to the value of I;} return 0;} [email protected]:~/my03$ [email protected]:~/my03$ [email protected]:~/my03$ [ Email protected]:~/my03$ [email protected]:~/my03$ [email protected]:~/my03$ cat makefile sdram.bin : head. S leds.carm-linux-gcc -c -o head.o head. sarm-linux-gcc -c -o leds.o leds.carm-linux-ld -ttext 0x30000000 head.o leds.o -o sdram_elfarm-linux-objcopy -O binary -S sdram_elf Sdram.binarm-linux-objdump -d -m arm sdram_elf > sdram.disclean:rm -f sdram.dis sdram.bin sdram_elf *.o[email protected]:~/my0
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Experimental study on SDRAM