FIFO data cache

FIFO data buffers:

FIFO (first Input firstly Output) an FIFO data buffer, the first to enter the data first read from the FIFO buffer, compared with the RAM has no external read and write address lines, the use is relatively simple, but only sequentially write data, sequential readout data, It cannot be read or written to a specified address by the address line, as in normal memory.

FIFO The role of the data buffer:

FIFO is generally used for data transmission between different clock domains, such as the one end of the FIFO is AD data acquisition, the other end is the PCI bus, so the FIFO can be used as a data buffer between two different clock domains. In addition, for different widths of the data interface can also be used FIFO, such as single-chip camera 8-bit data output, and DSP may be 16-bit data input, in the microcontroller and DSP connection can use FIFO to achieve data matching purposes.

FIFO data buffers are categorized by working clock domain:

According to the FIFO working clock domain, the FIFO can be divided into synchronous FIFO and asynchronous FIFO. Synchronous FIFO refers to the reading clock and the write clock for the same clock, the clock along the edge of the temporary simultaneous read and write operations; asynchronous FIFO refers to the read-write clock inconsistency, read-write clock is independent of each other. For asynchronous FIFO there are two general understandings, one is that the read and write operation does not use the clock, but the direct use of wr_en (write enabled) and Rd_en (read enabled) to control, and the other is in the FPGA and ASIC design, The asynchronous FIFO has a two-port FIFO of two clocks, which are read on the respective clock delay and can be read or written at the same time under two different clocks. Asynchronous FIFO in FPGA design summary occupies a lot more resources than synchronous FIFO, so try to use synchronous FIFO design. However, most peripheral interfaces in arm systems are asynchronous FIFO.

FIFO parameters of the data buffer:

FIFO width	The width is a FIFO read-write operation data bit, like MCU has 8-bit and 16-bit, ARM 32-bit and so on, the width of the FIFO is fixed in a monolithic IC, there is also optional, if the FPGA to implement a FIFO, its data bits, that is, the width can be defined by themselves.
FIFO depth	The deepth, which refers to how many n bits of data the FIFO can store (if the width is n). such as a 8-bit FIFO, if the depth is 8, it can store 8 8 bits of data, the depth of 12, you can store 12 8 bits of data. In the FIFO actual work, the full/empty flag of its data can control the continuation of the data write or read out. In a specific application it is also not possible to count the number of parameters of the exact required FIFO depth, which is more than the ideal state of writing speed than the reading speed is feasible, but in practice the FIFO depth is often greater than the calculated value. In general, according to the specific situation of the circuit, in the case of system performance and FIFO cost estimates a approximate width and depth can be. For applications where the write speed is slower than the read speed, the depth of the FIFO must be determined based on the readout data structure and the specific requirements of the readout data.
FIFO Full flag	A signal sent by a FIFO state circuit when the FIFO is full or is about to be full, to prevent the FIFO from continuing to write data to the FIFO, causing overflow (Overflow).
FIFO Empty flag	A signal sent by a FIFO state circuit when the FIFO is empty or will be empty, to prevent the read operation of the FIFO from continuing to read data from the FIFO, resulting in invalid data readout (underflow).
FIFO Read clock	The read operation follows the clock, reading the data at each clock along the coming time.
FIFO Write Clock	The clock that the write operation follows, writing the data as each clock comes along.
FIFO Read pointer	Point to the next read out address and automatically add 1 after reading.
FIFO Write pointer	Point to the next address you want to write, and automatically add 1 when you finish writing.

FIFO The difficulty of data buffer design:

The difficulty of FIFO data buffer design is how to determine the empty/full state of FIFO. In order to ensure that the data is correctly written or read out without the benefit or the state of the read empty, it is necessary to ensure that the FIFO is full and the write operation cannot occur. The read operation cannot be performed in an empty state. How to judge the full/empty FIFO becomes the core problem of FIFO design.

Vijay A. Nebhrajani "asynchronous FIFO Structure", two algorithms for FIFO empty/full flags are presented in this paper.

algorithm One : Construct a FIFO with a pointer width of n+1 and a depth of 2^n bytes (convert the gray code pointer to a binary pointer for a comparison of the sides). When the top of the binary code of the pointer is inconsistent and the other n bits are equal, the FIFO is full (in Clifford E. Cummings's article The Gray code is the first two bits are not the same, then the two-bit LSB is the same full, which is the same as the MSB in binary notation is different from the same as full).

Example: How a FIFO with a depth of 8 bytes works (using a pointer that has been converted to binary). Fifo_width=8,fifo_depth= 2^n = 8,n = 3, the pointer width is n+1=4. At first Rd_ptr_bin and wr_ptr_bin were "0000". A 8-byte data is written to the FIFO at this time. Wr_ptr_bin = "rd_ptr_bin=", "0000". Of course, this is the full condition. Now, suppose that 8 reads were performed, making rd_ptr_bin = "1000", which is the null condition. Another 8 writes will cause Wr_ptr_bin to be equal to "0000", but Rd_ptr_bin is still equal to "1000", so the FIFO is full condition. Obviously the start pointer does not need to be "0000". Assuming it is "0100" and the FIFO is empty, then 8 bytes will make Wr_ptr_bin = "1100", and Rd_ptr_bin remains "0100". This also indicates that the FIFO is full.

In Vijay A. Nebhrajani this "asynchronous FIFO structure" article explains how to use the gray code to set the condition of empty full, but did not say why the depth of 8 FIFO its read-write pointer to the 3+1 bit of gray code to achieve, and 3+1 bit of gray code can represent 16-bit depth, And the real FIFO is only 8 bits, what's going on? And this question is explained in Clifford E. Cummings's article.

Three-bit gray code can represent the depth of 8 bits, if in addition to the most MSB, then this bit plus the other three-bit gray code does not represent the new address, that is, the gray code of 0100 represents 7, and 1100 still represents 7, But Gray code in a 0-bit MSB after the loop into a 1-MSB loop, and then into a 0-bit MSB loop, the other three-bit code is still gray code, but this brings a problem, after the completion of the 0100 cycle, into 1000, they have two bits between them have undergone a transformation, Instead of 1 bits, so adding a MSB to the code in two places: 0100~1000,1100~0000 has a two-bit code change, so the code is not the real gray code. The added MSB is for the calculation of empty full flags. Vijay A. Nebhrajani article with gray code to binary, and then to the case of the Gray code to put forward empty conditions, after two conversions, and Clifford E. Cummings in the article directly under the Gray code condition to obtain the empty full condition. In fact, the two are the same, but the way of implementation is different.

algorithm two : The style #2 mentioned in Clifford E. Cummings's article. It divides the FIFO address into 4 parts, each with a height of two bits of MSB 00, 01, 11, 10 to determine whether the FIFO is going full or going empty (about to fill or blank). If the high two-bit MSB of the write pointer is less than the read pointer of the high two-bit MSB then the FIFO is "almost full", and if the high two-bit MSB of the write pointer is greater than the read pointer of the high two-bit MSB then the FIFO is "almost empty".

A method is also mentioned in the third part of the asynchronous FIFO structure of Vijay A. Nebhrajani, which is the direction sign and threshold. Set the FIFO capacity of 75% as the upper limit, set the FIFO capacity of 25% is the lower limit. When the direction flag exceeds the threshold, the full/empty flag is output, which is #2可谓是异曲同工 with the style mentioned in Clifford E. Cummings's article. They all belong to the conservative empty-full judgment. In fact, the output empty full flag FIFO is not necessarily really empty/full.

FIFO design is the most critical is the generation of empty/full flag algorithm, but whether it is accurate empty full or conservative empty is to ensure that the FIFO work is reliable.

absrtact : Firstly, it introduces the concept, application and structure of asynchronous FIFO, then analyzes the difficult problem and its solution to realize asynchronous FIFO, and presents a novel circuit structure based on the traditional design and its comprehensive simulation and FPGA implementation.

Keywords : Asynchronous circuit FIFO metastable Gray Code

1 Introduction to asynchronous FIFO

In modern IC chips, as the scale of the design continues to expand, a system often contains a number of clocks. One problem with multi-clock domains is how to design an interface circuit between asynchronous clocks. Asynchronous FIFO (first in first out) is a simple and quick solution to this problem. With asynchronous FIFO, real-time data can be transmitted quickly and easily between two different clock systems. In the aspect of network interface, image processing and so on, asynchronous FIFO has been widely used.

An asynchronous FIFO is an advanced first-out circuit that uses a portion of a data interface that needs to be produced to store and buffer data transfers between two asynchronous clocks. In asynchronous circuits, the probability of loss of data is not zero because the cycle and phase are completely independent between clocks. How to design a high-reliability, high-speed asynchronous FIFO circuit becomes a difficult point. This article describes one way to solve this problem.

As can be seen from Figure 1: The whole system is divided into two completely independent clock domains--read clock domain and write time domain; The FIFO storage media is a dual-port RAM that can be read and write concurrently. In the Writing clock domain section, the write address generates logic to generate a write control signal and a write address, and the read clock part generates logic to generate read control signals and read addresses from the read address. In the empty/Full flag generation section, the null/full flag is generated by the read-write address comparison.

2 Design difficulties of asynchronous FIFO

There are two difficulties in designing asynchronous FIFO: One is how to synchronize the asynchronous signal so that the trigger does not produce metastable state, and the second is how to design the control circuit of the empty, full and almost full signal correctly.

The following describes the specific methods of solving the problem.

2.1 the solution of metastable state problem

In the digital integrated circuit, the trigger should meet the setup/hold time requirement. When a signal is latched to the register, the value of the Q end is indeterminate and is fixed to high or low at unknown times if the signal and clock do not meet this requirement. This process is called metastable State (metastability). Figure 2 shows the asynchronous clock and the metastable state, and the Clka and clkb in the figure are asynchronous clocks.

The metastable state is bound to occur in the asynchronous FIFO. In the asynchronous FIFO, there is no time relationship between the input outside the circuit and the internal clock, so the setup/hold conflict is inevitable, and the signal passing between two unrelated clock domains within the circuit must also cause setup/hold collisions.

Although metastable is unavoidable, the following design improvements can reduce the probability of its occurrence to an acceptable level.

① to write address/read address using gray code. It is known from practice that the probability of synchronizing multiple asynchronous input signals is much greater than the probability of synchronizing an asynchronous signal. The Write address/read address consisting of the output of multiple triggers can be mined with gray code. Since gray code only changes one bit at a time, the use of gray code can effectively reduce the generation of metastable state.

The ② uses a trigger to synchronize the asynchronous input signal, and the bipolar trigger in 3 can reduce the chance of metastable to a very small degree. However, as shown in 3, this method simultaneously brings a first-level delay to the input signal, which needs to be noted when designing the clock.

2.2 generation of empty/full flags

The core part of the generation FIFO of the empty/full flag. How to correctly design this part of the logic, directly affect the performance of the FIFO.

Empty/Full flag is generated by the principle is: Write full not overflow, read empty not much read. That is, no matter what the study, there should be no read and write address at the same time on a memory address operation situation. When the read-write address is equal or one or more addresses, the full flag should be valid, indicating that the FIFO is full at this time, the external circuit should be the FIFO data. When the full signal is valid, write the data, according to the design requirements, or to maintain, or discard the re-hair. Similarly, the creation of an empty flag is also true:

Empty Flag <= (| Write address-read address |<= predetermined value) and (write address advanced read address)

Full Flag <= (| Write address-read address |<= predetermined value) and (Read address advance write address)

The most straightforward approach is to use a read-write address comparison to generate an empty full flag. 4, the empty/full signal is set when the difference between the read and write address is equal to a preset value. This method of implementation is simple in logic, but it is a relatively large combinatorial logic formed by the subtraction, thus limiting the speed of FIFO. Therefore, we generally only use the comparison logic of equality and inequality, avoid using the subtraction device.

Figure 5 is another common design in which the comparator only compares the read and write addresses for equality. There are two cases when the read-write address is equal: full or empty. Therefore, a parallel interval judgment logic is appended to indicate whether it is empty or full. This interval judgment logic divides the entire address space into several parts to indicate the relative position of the read-write address. This approach increases the speed of the entire circuit, but it also has its drawbacks. The main direct use of read and write address equals not equal to the comparison logic to carry out the empty/full flag judgment, can bring false.

3 novel FIF0 empty/Full flag control logic

3.1 analysis of Read-write addresses

From the above analysis of the FIFO, it can be seen that the direct subtraction from the address and the address of each other to produce an empty/full flag is not desirable. How do you simply make a direct comparison without increasing the complexity of the logic? This can be done by adding a delay to the address. Set read address is RD_BIN_ADDR, with read address rd_addr generate read address of gray code RD_NEXT_GRAY_ADDR, will rd_next_gray_addr a beat to get rd_gray_addr, then Rd_gray_ Addr a beat to get rd_last_gray_addr. In absolute time, rd_next_gray_addr, RD_GRAY_ADDR, rd_last_gray_addr These address relations, from large to small arrangement, and the difference of an address, 6.

The write address of the gray code is similar to the production, namely: Wt_next_gray_addr, Wt_gray_addr, wt_last_gray_addr. With these 6 gray codes for comparison, plus read and write enable, it is convenient and flexible to produce empty/full flag.

In the case of the empty flag null, the EMPTR flag should be set to valid (active high) when the read-write gray code address is equal or if there is still a deep word left in the FIFO and is not empty.

i.e. empty<= (RD_GRAY_ADDR=WT_GRAY_ADDR) and (read_enable=1) or empty<= (RD_NEXT_GRAY_ADDR=WT_GRAY_ADDR) and (Read_ enable=1)

The same analogy can be used to create logic of signs.

3.2 FIFO flag generation logic based on time-delay gray code

Figure 7 is the logic used to create and sign the address generated using the above thought. First, in the Address generation section, the resulting gray code address is added a delay, using its previous level address and the current read address for comparison. Secondly, when the empty/full flag is valid, an internal protection mechanism is used, which does not cause the read/write address to be increased and the reading and writing addresses are combined to operate on a storage unit.

3.3 Simulation Signal Waveform

A 256x8 FIFO is constructed using the idea of the circuit design of Figure 7, which is simulated by Modelsim. Figure 8 is the simulation waveform of the main signal to the reading space in the system.

Figure 6 The relationship between gray codes after delay

In Figure 8, Wdata for write data, rdata for reading data, WCLK for write clock, RCLK for read clock, rempty for empty signal, aempty for almost empty signal, rptr for read address wptr for write address, rgnext for next read address Gray code, Rbin read address binary , Rbnext is the binary code for the next read address.

As can be seen from Figure 8, since the reading clock is higher than the write clock, the read address gradually catches up with the write address, where the aempty signal indicates the proximity of the read address and the write address. When the signal is long enough to be caught by the trigger, the true NULL signal rempty valid.

4 analysis of the advantages of the circuit

As can be seen from Figure 7, the biggest bottleneck of this circuit is the sum of the delay of binary to Gray code and comparator. Because the delay of both combinational logic is very small, the speed of the circuit is very high. Tested, the clock frequency is up to 140MHz in Xilinx's FPGA. In addition, the asynchronous full signal is added with a one-stage latch, which outputs a reliable and stable flag.

Fig. 8 Simulation waveform diagram of the read-out condition

5 Summary

In the actual work, a 256x8 FIFO is implemented using the logic shown in Figure 4, Figure 5 and Figure 7 respectively. The integrated tool is SYNPLIFY7.0 and is routed from the foundation Series 3.3i layout to the wirtexev100ecs144 of Xilinx Corporation. Comparison of the performance indicators of the three are shown in table 1.

Table 13 Comparison of different designs

logical design mode	clock frequency/mhz	Valid results output frequency/mhz	slice number/each
	160	78.9	17
/td>	160	92	15
	160	140	13

Table 1 shows that the asynchronous FIFO shown in Figure 7 has a high circuit speed and small area, thus reducing the power consumption and improving the stability of the system.

FIFO data cache