270-vc709e Enhanced Xilinx Vertex-7 FPGA V7 xc7vx690t PCIeX8 interface card based on FMC interface

vc709e Enhanced Xilinx Vertex-7 FPGA V7 xc7vx690t PCIeX8 interface card based on FMC interface

first, the Board of Cards overview Based on Xilinx's FPGA xc7vx690t-ffg1761i chip, the board supports FMC connectors with PCIeX8, 64bit DDR3 capacity 2GBYTE,HPC, Board supports a variety of interface inputs, and software supports Windows. second, functional and technical indicators: 1, Standard PCI-E interface, support PCI-E 8x, support PCI-E 3.0. 2, the standard FMC-HPC interface, the Vadj level is 1.8V. 3, the front panel out of the 1-way SFP + optical module, the highest design speed of 10Gbps. 4, the board behind the 2-way SFP + optical module, the highest design speed of 10Gbps. 5, Standard JTAG interface. 6, support two groups of 64BIT,2GB DDR3. 7, the main frequency 1GHz, support 1.2GHz 8. Fast loading with BPI mode. 9, the device supports commercial grade, industrial grade. third, the interface test software: 1, DDR3 IP test, PCIe IP test; 2, million gigabit fiber network development 3, FMC on the high-speed ADC,DAC sub-card, and can provide a demonstration program. Iv. VIRTEX7-based PCI-E 30,000 Gigabit Ethernet product IP Development This board card is based on the Virtex7 xc7v690t-1ffg1761i, the design of the PCIe Backplane, the board features are as follows: 1, Standard PCI-E interface, support PCI-E 8x, support PCI-E 3.0. 2, the standard FMC-HPC interface, the Vadj level is 1.8V. 3, the front panel out of the 1-way SFP + optical module, the highest design speed of 10Gbps. 4, the board behind the 2-way SFP + optical module, the highest design speed of 10Gbps. 5, support two groups of 64BIT,2GB DDR3. 6, Standard JTAG interface. 7, support BPI mode fast loading. Xilinx-based V7 FPGA-developed PCIe DMA IP Supports 8.0Gbps (GEN3) at x8,x4,x2 and X1 hard cores, including Kintex-ultrascale and Virtex-7 gth type FPGAs Supports 5.0Gbps (GEN2) at x8,x4,x2 and X1 hard cores, including kintex-ultrascale,virtex-7 gth,virtex-7 gtx,kintex-7 GTX and Zynq-7045 types of FPGAs Supports 5.0Gbps (GEN2) at x4,x2 and X1 hard cores, including Artix-7 and Zynq-7030 types of FPGAs Compatible with PCIE3.0 protocol; maximum payload n Byte; support for MSI and INT messages Axi Interface: Bridge configuration can be done via the Axi4-lite slave interface External register configuration can be performed via the Axi4-lite Master interface Supports up to 4 AXI4 master interfaces Supports up to 4 AXI4 slave interfaces Supports up to 4 AXI4 stream input and stream output interfaces AXI4 Master,slave and Stream interfaces support 64bit,128bit and 256bit data AXI4 master and Slave interfaces can be configured as AXI3 interfaces Configuration: Operation of bridge configuration space via PCIe and/or axi4-lite slave interface Bridge Internal Register with 4KBytes Has a 4KBytes PCIe configuration space 8KBytes user-defined external register space DMA Engine: Supports up to 8 fully independent DMA engines Supports up to 4GBytes or infinitely long transmission lengths Supports up to 16 outstanding read requests and write requests Support Completion reordering Reconfigurable source and purpose, can be changed between PCIe interface, AXI4 master interface and stream input and output interface Flexible Scatter-gather DMA mode, including dynamic DMA control for each descriptor Optional DMA status report to descriptor for easy software management design Provides discrete DMA capabilities, direct DMA capabilities, and DMA channel management Xilinx V7 Series FPGA-developed TCPIP IP Core Characteristics: 1. Support for multiple 10G Macs 2. Each TCP hard-core stack supports 8 logical interfaces. Each interface can have a unique IP, physical address, VLAN ID, gateway, subnet mask. 3. Support for 9K bytes of extra long package 4. Support VLANs 5. Embedded ARP 6. Connect the 10G pma-pcs PHY with the Xgmii high-speed interface 7. A axi4-stream interface that works in 156.25MHz 64bit allows users to debug and use 8. The IP core can be configured via a 32bit axi4-lite slave protocol 9. User interface for 128bit axi4-stream working in 156.25MHz 10. TCP session mode for up to 128 concurrent clients or servers. Each session can be connected to any logical interface 11. Turn on specific flow control features for each session 12. User-Configurable TCP options: MSS, timestamp, VLAN PCP, VLAN DEI 13. If the packet length is greater than the value from the user application interface remote configuration (MSS), the load is automatically split. 14. Configurable TCP re-operation Memory: width, depth, internal or external This design scheme supports two modes of hardware board sales and IP sales. You can also delegate the design of the finished product. In addition to supporting the VIRTEX7 series, IP can also support the development of higher-grade chips such as the UltraScale series. Five application areas Software Radio processing Platform Graphic Image Hardware Accelerator Net FPGA

270-vc709e Enhanced Xilinx Vertex-7 FPGA V7 xc7vx690t PCIeX8 interface card based on FMC interface