80386 Summary of the protection Model (iii)

First, the general comparison of the 8086 and 80386 addressing

The 8086 logical address consists of a 16-bit segment address and a 16-bit intra-segment offset. Addressing method: The segment address is specified by the user program and is saved in the segment register. In the future, the program uses the offset address (the offset within the paragraph) directly. Memory addressing (how to get the physical memory address): 1. Obtain the corresponding segment address (save the segment register). 2. Get the offset address (this is usually given in the instruction). 3. After an operation rule a 4. Get the physical memory address

The logical address of 80386 is also divided into two parts: 16-bit Segment selection Sub + 32-bit segment offset. Addressing: The logical address (where the virtual address is reasonable) is determined at the time of program compilation (possibly the operating system, compiler, connector). Memory addressing: 1. Obtain the corresponding segment selector (in the Save Segment register). (segment selector is actually in the 16-bit segment register.) It's just a change of name. The following will explain why) 2. Get the offset address (this is usually given in the instructions). 3. After an operation Rule B 4. Get the physical memory address (if no paging)

From the above you can see that memory management from 8086 to 80386 is essentially the same. are addressed through the segment register and the offset address: The addressing method can be expressed as a segment register: [Intra-segment offset] different from 8086 to 80386 above in step 3, the Operation rules and offset address length changed.

Now specifically write down the address operation rules in step 3: Operation rule A (8086): 20-bit Physical address = Segment Address (16 bit) *10h + segment offset (16 bit) This is the legendary segment address left shift four bit + offset address to form a 20-bit physical address. Operation Rule B (8386): 1. Locate the Subgrade address (32-bit) 2.32-bit Physical address = Segment Base site (32-bit) + Intra-segment offset (32-bit) from the segment selector to change the name to 80386 because the Subgrade address is selected by the contents of the segment register. In fact, all this is still very simple. To be complicated, that's more than 80,386 of the computational steps. But don't worry. These addresses are accomplished by hardware without your own calculation.

The final note is 80386 more than a paging function, this feature is optional. If paging is enabled, the address is actually a linear address, and a transform is required to form a physical address.

Ii. related registers and data structures

This place can be a casual look (but very important in fact), do not understand the bypass. See below you can go back and check it out.

Descriptor descriptor a fixed structure of struct (struct) length is 8 bytes that is 64 bits, then what is the structure of the body? Used to describe a segment base address. This structure includes subgrade address, section length, and segment properties. This described Subgrade address is the Subgrade address in the above 32-bit Physical Address = Segment Base site (32-bit) + segment offset (32-bit). There are two types of descriptors, that is, the structure has two different structures (in fact, it contains almost the same content only a few small differences). A description of a data segment, code snippet, and stack segment, called a non-system descriptor, and the other is used to describe the LDT and TSS, (the LDT and TSS are described later) called the System segment descriptor.

The GDT Global Descriptor table, as its name implies, is a descripter. This table is stored in memory and is equivalent to a struct array. Each item of the array is the descriptor described above. This table can contain four kinds of information descriptors. 1. Global Data segment Code snippet stack segment, these segments are used by the general operating system kernel. (Each individual user task is described by the LDT, the LDT is followed by a description) 2. Description of the LDT the base address of the descriptor is the start location in the memory where the LDT is located 3. Description of TSS the base address of this descriptor is the origin of the 4 in the memory where TSS resides. Some door descriptors (call door, break door ...) It uses the non-system segment descriptor mentioned above, #2, #3, #4用的是系统段描述符. Different door buy descriptors, ldt,tss Although all use the system segment descriptor but some of these attribute values use pull to distinguish different descriptors. BTW:LDT,TSS are all part of each task, so the general pair appears in the GDT.

The GDTR Global Descriptor Descriptor Table Register (Global Descripter) GDTR is a register, and Ax BX. CS DS ... a concept. This registers a total of 48 bits. The 32-bit address indicates the location of the GDT in memory (which can be said to be a 32-bit physical address, if no paging is turned on), and the other 16 bits are the size of the GDT (the maximum number of GDT can be).

The local descripter Table of the LDT is similar to the structure of the GDT, except that the LDT simply contains a description of the snippet stack segment (which does not contain descriptions of TSS, and LDT) for each user task.

The LDTR Local Descriptor Table Register (Global descripter) LDTR and GDTR are also registers, except that it is only 16 bits in size. Why not and GDTR not 48-bit it. The reasons are as follows: 1.GDT is generally only one in a multitasking system, so the base address is determined by a GDTR and will hardly change after that. But the number of LDT can be equal to the user's task, that is, each user task may have their own ldt, here Ldtr inconvenient and gdtr the same as the use of a 48-bit register to give the base address, because the task of the switch before the base address is lost. The task will not be switched back. or the task switch back to rebuild your own LDT, the efficiency is very low. A 16-bit selector is stored in 2.LDTR, which addresses the base address of the LDT in the GDT based on this selector. In other words: the base address of the Global Descriptor Table (GDT) is present in the GDTR (that is, the GDT is positioned by GDTR), while the base address of the local descriptor Tables (LDT) is present in the GDT, as described in the list of GDT (note that As we said earlier, the descriptor entry in the GDT includes a description of the LDT segment. LDTR as a selector, the LDT as a description of the advantage in the GDT is that the local descriptor of each user task (LDT) memory address is placed in the GDT, so that when the task is switched to change the selector can be achieved by the LDT switch, and because each LDT in the GDT has a description, No loss, convenient task switching back.

The TR Task Register (Task Register) is a 16-ldtr, similar in function to an index in the Global Descriptor List (GDT). The difference is that the description of the TR selection is no longer a section of the LDT. The TR selection descriptor describes a task status segment (Tss:task status Segment).

TSS task status Segment (Task State Segment) as previously stated, the task status segment (TSS) is described in the GDT. What does the task status segment do? The task status segment is a data structure in memory. This structure holds information related to the task. The register content (CS EIP DS SS ...) that will be used for the current task when a task switch occurs. The selection of the LDT is preserved in the TSS so that the task can be switched back to use.

In fact, in addition to the above register, there are some inaccessible hidden registers, these hidden registers are actually high-speed buffer registers, can ignore its existence. In order to reduce the complexity of comprehension is not written. The explanation is given in the following section.

Selector Select a total of three types by use (in fact, because the format is exactly the same), the selector in 1.TR, used to select a TSS descriptor from the GDT. A selector in 2.LDTR that is used to select a LDT descriptor from the GDT. 3. The logical address in the user program (virtual address, this address 48 bits = 16 bit Select child + 32 bit offset address) contains the selectors. The descriptor (data segment, code snippet ...) used to select the segment in the LDT (or GDT) used by the program. This selector is determined by the compilation or connection or the operating system.

Three, paging

CR0 save a page base A, the linear address is transformed into a physical address by a two-level page: See figure below (excerpt from 80386 manual).

The linear address is divided from high to three sections high 10 bits B, middle 10 bits C, end 12 bits d. The transformation process is no longer described (the language description may seem complex, in fact, simple). Here is a simple Transformation formula: page base address = A;  Page Base Address = page Base + B * 4; /* Check the table of primary directory, at (page base +b*4) to get the base address of the two-level page table, where the equals point is the table/page base = page Base + C * 4;/* Check the two-level catalog page table, at (page base +b*4) to obtain a physical base address, where the equals is the table * + D; Why X4? Because the page table is aligned by 4-bit. Page Catalog entry after four bit not used. By the way, select the sub-Gdt/ldt index is: Descriptor address = base+selector*8. Why X8. Similarly, a Gdt/ldt of 8 bytes.

Iv. 80386 memory management and task switching (specific process)

A 80386 operating system runs two user tasks A and B, as shown in the following diagram:

This process does not draw a hidden register that includes inaccessible hide-in-door. In fact, after TR,LDTR, there is a 64-bit (content and descriptor-like), externally inaccessible buffer register. The content is the descriptor corresponding to the current selection. This will only go to the in-memory GDT index when switching tasks. The CPU directly reads a descriptor that corresponds to a TR or LDTR stored in a buffer register when executing code or data addressing.

Task A runs

Task B Runs

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