8-3 Encoder, Verilog implementation of 3-8 decoder

In a digital system, the information is often transformed into bits of binary code, because the data is processed using binary operations. In a logic circuit, the signal is output in the form of a high, low level. Encoder: The implementation of coded digital circuit, the input of each high and low level signal into a set of corresponding binary code.

A 3-bit binary encoder with an input of 8 active high signals and an output code of the original code output is designed.

Simplified logic expression: By the logical expression can be obtained, the ordinary 8-3 encoder or the door can be achieved. The corresponding Verilog program is as follows:

Modulemb_83 (x, y);input[7:0]x;Output[2:0]y;Reg[2:0]y; always@ (x)begin Case(x)8'b00000001:y=3'b000;//when X=8 ' b00000001, then the y output is 3 ' b0008'b00000010:y=3'b001;//when X=8 ' b00000010, then the y output is 3 ' b0018'b00000100:y=3'b010;//when X=8 ' b00000100, then the y output is 3 ' b0108'b00001000:y=3'b011;//when X=8 ' b00001000, then the y output is 3 ' b0118'b00010000:y=3'B100;//when X=8 ' b00010000, then the y output is 3 ' B1008'b00100000:y=3'b101;//when X=8 ' b00100000, then the y output is 3 ' b1018'b01000000:y=3'b110;//when X=8 ' b01000000, then the y output is 3 ' b1108'b10000000:y=3'b111;//when X=8 ' b10000000, then the y output is 3 ' b111default: y=3'b000;EndcaseEndEndmodule

The encoder has a disadvantage, that is, at a certain time only allowed to have a valid input, and if there are two or more than two input signal required to encode, the output must be chaotic, error occurred. In order to solve this problem, a priority encoder is introduced. The function of the priority encoder is to allow the input signal at several inputs at the same time, the encoder in accordance with the input signal pre-scheduled priority, only a number of simultaneous input signals with a high priority of a signal encoding.

The corresponding truth table is

Corresponding Verilog program: (Input signal: i[7:0]; input enable end: EI; output signal end: y: [2:0]; output enable terminal EO; Priority flag end GS)

Moduleyxbm_83 (y,eo,gs,i,ei);input[7:0I//8-bit input iinputEi//enable input-eiOutputEo,gs;//enable output end EO, Priority flag end GSOutput[2:0] y;//3-bit output yReg[2:0] y;//3-bit output register yRegEo,gs;//Enable output Register, always@ (I,ei)//level trigger mode, when I and EI have changed, do the followingbeginif(ei==1'B1)//When EI is 1beginy<=3'b111;gs<=1'B1;eo<=1'B1;EndElsebeginif(i[7]==1'B0)//When the 8th of I is 0beginy<=3'b000;gs<=1'B0;eo<=1'B1;EndElse if(i[6]==1'B0)//when the seventh bit of I is 0beginy<=3'b001;gs<=1'B0;eo<=1'B1;EndElse if(i[5]==1'B0)//When the 6th bit of i is 0beginy<=3'b010;gs<=1'B0;eo<=1'B1;EndElse if(i[4]==1'B0)//When the 5th bit of i is 0beginy<=3'b011;gs<=1'B0;eo<=1'B1;EndElse if(i[3]==1'B0)//When the 4th bit of i is 0beginy<=3'B100;gs<=1'B0;eo<=1'B1;EndElse if(i[2]==1'B0)//When the 3rd bit of i is 0beginy<=3'b101;gs<=1'B0;eo<=1'B1;EndElse if(i[1]==1'B0)//When the 2nd bit of I is 0beginy<=3'b110;gs<=1'B0;eo<=1'B1;EndElse if(i[0]==1'B0)//When the 1th bit of i is 0beginy<=3'b111;gs<=1'B0;eo<=1'B1;EndElse if(i==8'b11111111)//When I is 8'b11111111 Timebeginy<=3'b111;gs<=1'B1;eo<=1'B0;EndEndEndEndmodule

Results of the timing simulation:

Decoder (Decoder): The process of translating the specific meaning of a code state into a decoding. Decoder: The logic circuit that realizes decoding operation is the circuit that transforms one kind of code into another code.

Decoder and encoder diagram:

To design a 3-8 decoder with three enable terminals:

The truth table is: 3-bit encoded input a[2:0], enable input terminal g1,g2,g3; output signal: 8-bit encoded output Y[7:0].

Moduleym_3_8 (a,g1,g2,g3,y);input[2:0A//3-bit 2-input coded inputsinputG1,G2,G3;//3 Enable inputsOutput[7:0] y;//8-bit coded outputReg[7:0] y; always@ (AorG1orG2orG3)//level trigger Modebeginif(g1==0) y=8'b11111111; If G1 is 0, the y output is 11111111Else if(g2==1) y=8'b11111111; If G2 is 1, the y output is 11111111Else if(g3==1) y=8'b11111111; If G3 is 1, the y output is 11111111Else Case(a[2:0])//determine the value of a and give y by the value of a//Setting output Values3'b000:y[7:0]=8'b11111110;3'b001:y[7:0]=8'b11111101;3'b010:y[7:0]=8'b11111011;3'b011:y[7:0]=8'b11110111;3'b100:y[7:0]=8'b11101111;3'b101:y[7:0]=8'b11011111;3'b110:y[7:0]=8'b10111111;3'b111:y[7:0]=8'b11111111;EndcaseEndEndmodule

8-3 Encoder, Verilog implementation of 3-8 decoder