Assembly language Wang Shuang

Assembly

Wang Shuang

Directory

Assembly... 1

Wang Shuang ... 1

Chapter One: Basic knowledge

Chapter II: Registers

Chapter III register (Memory access)

The first procedure of the fourth chapter

The sixth chapter contains multiple segments of the program

Seventh. More flexible ways to locate memory

The eighth chapter two basic problems of data processing

Chapter One: Basic knowledge

Assembly language: What is assembly language? Why learn assembly language? Learning assembly language is learning what?

Early morning use of machine language, but the machine language is difficult to understand and difficult to use, so there is assembly language. That is, the use of easy-to-understand assembly instructions to replace all binary 0 and 1 machine instructions.

Then there is the compiler, which translates the assembly instructions into machine instructions.

Neither the machine instruction nor the assembly instruction can be separated from the specific hardware design and the internal structure, and the high-level language is produced without portability.

Assembly language development so far, by the 3 types of directives.

1, assembly instruction: That is, the machine code mnemonic, has the corresponding machine code

2, pseudo-directive: there is no corresponding machine code, there is compiler execution, the computer does not perform

3, other symbols: such as: + 、-、 *,%, etc. have compiler recognition, no corresponding machine code

Assembler language is the core of assembly instructions, it also determines the characteristics of assembly language

What is CPU is the processing of instruction and data!

Where instructions and data are stored is memory

CPU to complete the action of specific instructions and data, then the access will interact with the memory

1, the address of the storage unit (address information)

2, the device selection, read or write commands (control information)

3. Read or write data (data information)

Address bus: Determining addressing capability

Data bus: Determines the number of data bits in a single transmission

Control bus: Determines how much control the CPU provides to external devices, i.e. the CPU's ability to control external devices

Bottom line: The CPU allocates the corresponding memory address space for the specific external device and controls it through various controllers (interface cards).

8086 address bus width is 20, (0~220) memory address space is 1MB

80386 address Bus section 32, (0~232) memory address space of 4GB

Big B Small B, default one memory space size is 1BYTE = 8bit is the difference between byte and bit

Why is a memory unit 8 bits? Look at the principles of computer composition.

Chapter II: Registers

A typical CPU is composed of an operator register and a controller, the operator is responsible for the storage, the controller controls the individual devices, and the internal bus is responsible for connecting the devices to pass data between them.

For a programmer, the main CPU device is a register, and we can actually control the CPU by changing the contents of various registers.

8086CPU has 14 registers: AX BX CX DX

CS DS SS ES

SI DI SP BP IP PSW

How does the CPU address memory?

20-bit Address line 16-bit wide register

8086 using Physical address = Segment Address X16 + offset address method

done by the address adder

The essential meaning of "segment address x 16 + offset address = Physical Address" is that the CPU accesses memory with a base address (segment address X16) and an offset address relative to the underlying address to give the physical address of the memory unit

Note: The size of the segment fragment segments of the segment stack segment ... Nothing to do with memory memory is just memory

It's all just how the CPU operates on our schedule.

Segment address naturally provided by four segment registers CS DS ES SS

CS and IP

CS for the code segment Register IP is the instruction pointer register CS:IP the content pointed to as the current instruction execution

CS:IP Instruction Segment Register

MOV Transfer Instructions

The instructions for the JMP transfer instruction to modify CS IP content are collectively referred to as transfer instructions

JMP segment Address: offset address

A valid register in JMP: Modify the IP with the value in the Register

JMP 2ae3:3 after execution: cs=2ae3h ip=0003h

Jmp Ax, prior to execution: ax=1000h cs=2000h ip=0003h

After execution: ax=1000h cs=2000h ip=1000h

The second chapter explains the logical structure of 8086CPU, the method of forming physical address, related registers and some instructions from the angle of how the CPU executes the instruction.

About the Debug experiment

1. R View Change Register Content-R, R AX

2, D view in-memory content D 1000:0 (128 memory units at the beginning of a specified address)

You can continue d after using D

D 1000:0 10

3, E Modify the contents of the memory e 1000:0 0 1 2 3 4 5 6 7 8 9

4, U view machine code corresponding assembly instruction

5. T executes one or more instructions

6, a in the form of assembly instructions in memory to write machine code

Experiment One:

View and modify the contents of registers in the CPU: R instruction

View in-memory content: D command

Modify the contents in memory: E command (can write data, instructions, in memory they actually no difference)

Interprets in-memory content as machine instructions and corresponding assembly instructions: U command

Executes the instruction at the memory unit pointed to by the CS:IP: T instruction

Write instruction to memory in assembly form: a instruction

Chapter III register (Memory access)

BYTE unit

Word Unit

DS and [address]

DS is typically used to store the segment address to access data

Mov bx,1000h

Mov DS,BX

Mov Al,[0]

[...] Represents a memory unit data representing the offset address of a memory unit automatically taking DS as a segment address

Thinking: Write a few instructions to transfer the AL data to the memory unit at 10000H

ie: mov al,[0] mov [0],al

MOV Memory Unit address, register name

So far:

MOV Registers, data

MOV Registers, registers

MOV register, Memory unit---MOV segment register, memory unit

MOV memory unit, register---MOV memory unit, Segment register

MOV segment Register, register-mov register, segment register

Chapter III Learning registers from the memory access perspective

Word cell n Address Word unit

8086CPU does not support direct data into the segment register to use a register to relay

This is a hardware design problem, no need to delve into

Mov bx,1000h

Mov DS,BX

Stack

The stack is a special kind of access to the storage space, the particularity is that the final entry into the space of data first out.

LIFO last on first out LIFO

Into the stack out of the stack

CPU provides stack mechanism

So we can use a piece of memory as a stack.

The most basic two instructions are PUSH (into the stack) POP (out of the stack)

Two register segment Register SS and register SP are provided accordingly

The segment address at the top of the stack is placed at any time in the SS, Ss:sp points to the top element of the stack

PUSH and Pop are the addresses that the CPU gets the top of the stack from the SS:SP

The top of the stack rises from the high address in the end address direction.

SS:SP next cell pointing to the highest address cell in the stack space

CPU is not responsible for cross-stack operation

Push Register

Pop Register

Stacks are also part of memory

Naturally there

PUPSH Memory Unit

Pop Memory Unit

PUSH Segment Register

POP Segment Register

Write memory after changing SP

Change SP after reading memory

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The first procedure of the fourth chapter

1. Edit pre-processing compile link execution (load in memory)

Pseudo-directive format:

XXX segment

XXX ends

End Assembler's closing tag

Assume "Suppose" in some cases, you can associate a segment register with a section

DOS Program loading process

The purpose of the Learning assembly is to use the assembly language to program and understand the basic working mechanism of the bottom of the computer, and then control the computer arbitrarily.

The fifth chapter [BX] and loop

1, [BX] and [0] Similar segment addresses are also in the DS

2, Loop loop

3. Definition of Descriptive symbol "()"

(ax) represents the content in AX

4, the Convention idata represents the constant

@ to a [BX] what do you mean???

Loop instruction Execution Process

1, (CX) = (CX)-1

2, to determine the CX value is not 0 to go to the label execution, 0 down execution

Consider the question: calculate the number in the ffff:0006 unit multiplied by 3, and the result is stored in the DX.

Debug and MASM handles mov a1,[0] in different ways

Segment Prefix

The sixth chapter contains multiple segments of the program

Seventh. More flexible ways to locate memory

The eighth chapter two basic problems of data processing

Chapter Nineth Principle of transfer instruction

Intra-segment transfer

Inter-segment Transfer

Short transfer

Near transfer

[1]

Assembly language Wang Shuang