Digital Video BASICS (2)

2. Commonly Used Digital Video Standard 2.1 bt656

First, you must understand the waveform of the video signal simulating PAL/NTSC:

To transmit digital video data, first we need to digitize the analog video signal to obtain the YUV value of each pixel. Generally, the yuv422 format is used, and only the image data cannot be transmitted, it also needs to transmit row synchronization, field synchronization, parity field signals, and when each line of images starts. In this way, the receiver can correctly receive and understand data and obtain video reproduction.

The SAV (effective video start) and Eav (effective video end) codes reflect the synchronous signal of the simulated video. Starting from the delimiters ff, 00, and 00, the delimiters of these three bytes cannot exist in the video data. XY is a state word. Each digit is defined as follows:

Sometimes we can see that the difference between bt.601 and 656 is that synchronization information is missing in the data stream. Therefore, you must have synchronized information such as Hs, VS, fied, and De to transmit digital videos completely.

In most cases, we use 8bit bt656, and the standard itself supports 10bit.

Bt656 mainly targets SD videos such as PAL/NTSC. The clock frequency is 27 MHz. Note that the sample frequency is 12.5 MHz in gray scale and the color is 6.25 MHz.

With the development of HD videos, the bt1120 standard has been introduced. It is similar to bt656, but the clock frequency is higher, so it is suitable for the transmission of HD videos.

2.2 openldi and cameralink2.2.1 openldi

Openldi: Open LVDS display intrerface transmits videos through LVDS signals.

Learn about LVDS: Low-voltage differentialsignaling. Low-voltage differential signal.

LVDS provides extremely high bandwidth and can reach several GB.

Timing of VGA signal simulation:

Openldi provides the following transmission methods:

(1) 18bit unbalanced single pixel

(2) 24-bit unbalanced single pixel

(3) 18bit dual-pixel imbalance

(4) 24-bit dual-pixel imbalance

(5) 18bit single-pixel balancing Mode

In the balancing mode, in addition to pixels and control information, a bit is added for each cycle. This bit is called the DC balancing bit (dcbal: DC balance ). The purpose of the dcbal bit is to minimize the DC offset on the signal line. In order to minimize the DC component, it is necessary to modify the transmitted data. If the data has not been modified, dcbal = 0. Otherwise, dcbal = 1.

There are also 24-bit single-pixel balancing mode and 18-bit and 24-bit dual-pixel balancing modes.

Because the balancing mode is rarely used, the specific algorithms are not described here. See related documents.

The openldi clock may not be high, but the frequency on the data line is very high. This is worth noting.

2.2.2 overview of cameralink2.2.2.1

The openldi standard defines the video transmission mode, and adds some control signals, communications, and connector definitions to form the cameralink standard. The maximum clock frequency of cameralink is 85 MHz.

Cameralink has five configurations: Because the video resolution is getting higher and higher, that is, the pixel clock is getting higher and higher. For example, the single-color [email protected] Point frequency is 25.175 MHz (lite ), color [email protected] The dot frequency is 65 MHz (base), color [email protected] The dot frequency is 108 MHz (medium), so, different configurations are used to meet the video transmission requirements of different resolutions and precision. It is equivalent to a constant speed, adding lanes to increase the traffic flow.

L lite: supports 10 bits, ports a and B, and 1 cable connector

L Base: supports 24-bit, port A, B, and C, and one cable connector.

L medium: supports 48bit, port A, B, C, D, E, F, and two cable connectors.

L full: supports 64bit, port A, B, C, D, E, F, G, H, two cable connectors

L 80 bit. Supports 80 bits, port A, B, C, D, E, F, G, H, I, J, and two cable connectors.

Connector definition:

Cameralink signal:

In addition to data channels, there are:

(1) Four enable signals:

L fval: the frame is valid (fval), which indicates a valid row.

L lval: the row is valid, and the row is highly valid, indicating the valid pixel.

L dval: The data is valid. A high value indicates that the data is valid. 80-bit configuration. This signal is used to transmit data.

L spare: standby. 80-bit configuration. This signal is used to transmit data.

(2) Configure base/medium/full/80bit and the following camera control signals. For lite configuration, there is only one cc control signal.

(3) communication: the baud rate must be at least, one start bit, one stop bit, no parity check, and no handshake signal.

L sertfg: The difference pair of serial communication and the anti-frame capture device. For lite configuration, this signal is allocated to a difference pair carrying image data. See bit allocation.

L sertc: Serial Communication differential pair, de-camera.

The concept of Port: a port is 8-bit wide. From the signal connection point of view, one port can transmit 8-bit data, but there is no rule on what the 8-bit data is.

The concept of TAP: tap indicates a type of data, such as red data, green data, or blue data, gray data, idol data, or odd pixel data. For example:

1) use a base configuration to transmit the 24-bit RGB data. Each data in RGB is 8-bit, so we say it is three taps, each of which is 8-bit.

2) If we use a medium configuration to transmit dual-pixel RGB, And the RGB data is 8 bits, we will say that there are 6 taps, each of which is 8 bits.

3) If we use lite configuration to transmit black and white images, and the brightness is represented by 10 bits, we will say one tap, each of which is 10 bits.

The cameralink standard should clearly define the following content:

1) We know that the image data to be transmitted is composed of one or more taps. First, we need to define how each of these taps is allocated on the port, this is the bit assignment defined in section 2.2.2.1 ).

2) define each bit of the port and the phase in which lval, fval, fval, and spare are in the LVDS clock period, that is, the relationship between each port and the Rx/TX foot of the transceiver. This problem is defined in Bit Allocation of 2.2.2.2.

3) The standard also defines the channel connection on which each port is located, or on which chip, or on X or Y or Z connection channels? This is defined by the configuration diagram in section 2.2.2.3.

2.2.2.1 Bit Allocation (bit assignment)

2.2.2.2 bit location (Bit Allocation)


2.2.2.3 hardware routing and block diagram