FPGA composition, working principle, and development process

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Author: loongembedded (Kandi)

Time: 2012.1.7

Category: FPGA development

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Note: The following description is based on the FPGA chip of the Altera series. It is the first time to learn FPGA. Some of the content is summarized by reference to some documents, and there are still few personal analyses and insights.

 

1. FPGA Overview

FPGA, short for field programmable gate array, is a field programmable gate array. It is a product of further development on the basis of programmable devices such as pal, gal, and EPLD. As a semi-customized circuit in the specialized Integrated Circuit (ASIC) field, it not only solves the shortcomings of the custom circuit, but also overcomes the shortcomings of the limited number of door circuits of the original programmable device.

 

2. FPGA chip Structure

FPGA chip consists of three parts: IOE (input output element, input output unit), lab (Logic Array block, logical array block, which is referred to as configurable Logical Block CLB for XILINX) and interconnect ).

 

2.1 IOE

IOE is the physical interface between the chip and external circuit. IOE is used to drive and match input/output signals with different electrical characteristics, for example, from basic lvttl/lvcmos interfaces to PCI/LVDS/RSDs and even various differential interfaces, from 5 V compatible to 3.3 V/2.5 V/1.8 V/1.5v level interfaces, the following is the IOE structure of the cyclone IV ep4ce115f29 Device of Altera.

Figure 1 IOE structure of ep4ce115f29

Fpga ioe is classified by group. Each group can independently support different I/O standards. through flexible configuration of software, different electrical standard and I/O physical characteristics can be matched, in addition, the drive current size can be adjusted to change the up/down resistance. The Cyclone IV device has 8 Io blank (Group). For details, see:

Figure 2 Io Group of the cyclone IV Device

 

2.2 lab

Lab is the basic logic unit of FPGA. Its actual quantity and characteristics vary according to the devices used, the layout of each lab of ep4ce115f29 includes 16 Le, lab control signal, le carry chains, register chains, and Local Interconnect. Its lab structure is as follows:

Figure 3 lab Structure

Le is the smallest logical unit of the cyclone IV device. Each le consists of LUT and registers,

Figure 4 Structure of Le

Look-up-table (LUT) is essentially a static memory SRAM. Currently, FPGA uses LUT with four inputs, each LUT can be considered as a ram with a 4-digit address line of 16x1. When we describe a logical circuit through a schematic or HDL language, FPGA development software automatically calculates all possible results of the Logical Circuit and writes the results to ram in advance. In this way, when FPGA is working, each input signal performs a logic operation, which is equivalent to inputting an address for lookup, finding out the content corresponding to the address, and then outputting it.

Figure 5 implementation principle of LUT

 

2.3 Interconnect

FPGA has many internal connections. According to the description in the data manual, figure 3 shows row interconnect, column interconnect, direct link interconnect, and Local Interconnect and register chain Interconnect (the connection line connecting registers ).

 

The internal connection lines are connected to all the units in the FPGA, and the length and process of the connection lines determine the driving capacity and transmission speed of the signal connection lines. In actual development, the designer does not need to directly select a connection line. The layout manager can automatically generate a logical network table based on the input table) select a connection line to connect the topology and constraints of each logical unit. Therefore, in essence, the use of wiring resources is closely and directly related to the design results.

 

3. Working Principle of FPGA

FPGA uses a small search table (16 × 1ram) to implement the combination logic. Each search table is connected to the input end of a D trigger (see figure 4 ), the trigger then drives other logic circuits or drives I/O, thus forming a basic logic unit module that can realize both the combined logic function and the time series logic function, these modules are connected to each other using metal connections or I/O modules. FPGA logic is implemented by loading Programming Data to internal static storage units, the values stored in the memory unit determine the logical functions of the logical unit and the connection mode between modules or between modules and I/O, and ultimately determine the functions that can be implemented by FPGA, FPGA allows unlimited programming.

 

4. FPGA development process

Schematic diagram and HDL (Hardware Description Language) are the two most commonly used methods for describing digital hardware circuits, among them, the HDL design method has better portability, versatility, and the features of module division and reusability. It is widely used in current engineering design, the development process for FPGA familiar circuit design is based on HDL.

Figure 6 FPGA development process

1) System Function Design

Before designing the system, we must first make preparations for Scheme Demonstration, system design, and FPGA chip selection. Based on the task requirements, such as system indicators and complexity, the system engineer balances the working speed with various resources and costs of the chip, and selects a reasonable design scheme and a suitable device type. Generally, the top-down design method is used to divide the system into several basic units, and then divide each basic unit into the basic units at the next level, until you can directly use the EDA component library.

 

2) RTL-level HDL design

RTL level (register transfer level, register transfer level) indicates that details of registers and combined logic are not followed (for example, how many logic gates are used and the connection topology of logical gates ), describe how data flows between registers and how to process and control the data flows. The RTL level is more abstract than the door level, and is simpler and more efficient. The biggest feature of the RTL-level architecture is that it can be integrated into a door-level network table directly with comprehensive tools. The RTL-level design directly determines the system's functions and efficiency.

 

3) RTL-level simulation

Also known as function (behavior) simulation, or integrated pre-simulation, it is to verify the logic function of the circuit designed by the user before compilation. At this time, the simulation has no delay information, only preliminary functions are checked. Before simulation, you must first use the waveform editor and HDL to create a waveform file and a test vector (that is, combine the input signal concerned into a sequence ), the simulation results generate a report file and the output signal waveform, from which you can observe the signal changes of each node. If an error is found, the design modification logic design is returned. Commonly used tools include Modelsim of model tech, VCs of sysnopsys, NC-Tilde of cadence, and NC-VHDL. Functional simulation is not a required step in FPGA development, but is the most critical step in system design.

 

To improve the efficiency of functional simulation, we need to establish a test platform testbench. The test incentive is generally described in the behavior-level HDL language, where RTL-level modules can be integrated, it is a sub-set of the behavior-level module.

 

4) Comprehensive

The so-called synthesis is to convert the description of a higher abstraction level into a lower description. The logical connections generated based on the objectives and requirements are optimized comprehensively to make the hierarchical design flat for FPGA layout and wiring software. At the current level, integrated optimization (synthesis) refers to compiling design input into a logical connection network Table consisting of basic logical units such as gate, or gate, non-gate, ram, and trigger, it is not a real door-level circuit. Real and specific door-level circuits are generated based on the Integrated standard door-level structure network table by leveraging the layout and wiring functions of FPGA manufacturers. In order to be converted to a standard portal-level structured network table, the compiling of the HDL program must conform to the style required by the specific synthesizer. Because the integration of the gate-level structure and RTL-level HDL program is a mature technology, all the integrators can support this level of synthesis. Common integrated tools include Synplify/Synplify from synplicity.
Pro software and integrated development tools released by FPGA manufacturers.

 

5) Door-level simulation

It is also called integrated post-simulation. After integration, the simulation check results are consistent with the original design. During simulation, the standard delay file generated by the synthesis is reversed to the synthesis simulation model to estimate the impact of the door delay. However, this step cannot estimate the line latency. Therefore, there is still a certain gap with the actual situation after wiring, which is not very accurate. The current integrated tools are relatively mature and can omit this step for general design. However, if the circuit structure and design intent are found to be inconsistent after layout and wiring, you need to go back to the integrated simulation to confirm the problem. The software tools introduced in functional simulation generally support integrated post-simulation.

 

6) Layout and wiring

The purpose is to configure the integrated Logical Network table to a specific FPGA chip and match the engineering logic and timing with the available resources of the device. Layout and wiring are the most important process. layout rationally configures the hardware primitives and underlying units in the logical network table to the internal hardware structure of the chip, in addition, you often need to choose between the optimum speed and the optimum area. Based on the topological structure of the layout, the cabling properly and correctly connects various components using various connected Resources in the chip. You can also simply understand the layout and wiring as a rational configuration of FPGA internal Lookup tables and register resources. The layout can be understood as a selection of optimal resource combinations that can achieve the design of network tables, wiring is to connect these search tables and register resources in the optimal way.

 

At present, the FPGA structure is very complex, especially when there are timing constraints, you need to use the timing-driven engine for layout and wiring. After the wiring is completed, the software tool automatically generates a report to provide the usage of each part of the resources in the design. As only FPGA chip manufacturers have the best understanding of the chip structure, the layout and wiring must be the tool provided by chip developers.

 

7) timing simulation

It refers to marking the delay information of the layout and wiring to the design network table to detect whether there are any time series violations (that is, it does not meet the time series constraints or the inherent time series Rules of the device, such as the establishment time and retention time) symptom. Timing simulation provides the most comprehensive and accurate latency information, which can better reflect the actual operating conditions of the chip. Because the internal latency of different chips is different, different layout schemes also have different effects on the latency. Therefore, after layout and wiring, it is necessary to conduct timing simulation on the system and each module, analyze the timing relationship, estimate the system performance, and check and eliminate the risk of competition.

 

8) FPGA board-level debugging

The programmer downloads the configuration file after layout and wiring to FPGA to program its hardware. The configuration file is generally in. POF or. Sof format. The download methods include as (active), PS (passive), and JTAG (Boundary Scan.

 

Logic Analyzer (LA) is the main debugging tool designed for FPGA. However, it requires a large number of test pins and La is expensive. Currently, mainstream FPGA chip manufacturers have provided embedded online logic analyzers (such as chipscope in Xilinx ISE, signaltapii in Altera quartuⅱ, and signalprob) to solve these contradictions, they only need to occupy a small amount of logical resources on the chip and have high practical value.