FPGA configuration method

FPGA supports multiple configuration/loading methods. It can be roughly divided into two types: active and passive. Active loading refers to the configuration process controlled by FPGA, and passive loading refers to FPGA only passively receiving configuration data.

The most common passive configuration mode is to download bit files using JTAG. In this mode, the device that initiates the operation is a computer, and the data path is a JTAG. FPGA passively receives the data and updates the FPGA configuration according to the required operation. However, it is very flexible for the upper computer to obtain configuration data, which may be generated by running the EDA tool locally or by a network/USB storage device.

Active configuration means that FPGA is dominant in the configuration process. It actively initiates read/write operations on flash and obtains configuration information for configuration.

The following uses the built-in flash burning operation of the EDA tool as an example to analyze the specific burning process.

Generally, the complete process is:

1. The host machine initiates configuration and the FPGA passively receives data for reconfiguration. The configuration mode is the JTAG-based Passive configuration mentioned above. The result of this operation is to configure FPGA as a flash reader.

2. After the configuration is complete, the host computer starts to send/receive flash data, and the data channel is JTAG. After FPGA receives data through JTAG, it initiates read/write operations on flash as needed, and writes the data to flash to complete the update. This process is the flash update process. Flash only receives FPGA control during the flash burning process.

3. After the flash is updated, You can reconfigure the FPGA when appropriate (for example, re-power-on or power-off). The FPGA will start the Active configuration process and read the configuration data from the flash to complete the loading.

In Intel (Altera) mode, the file suffix is JIC, and the full name is JTAG indirect configuration file. Direct translation is a JTAG indirect configuration file. On the programmer interface of Quartus, after the JIC file is added, you can see that there is a factory default SFL image, which is the image that configures FPGA as the flash controller.

Depending on the configuration, there are two types: Active update and passive update.

If it is a passive update, a device is actively initiated during the configuration process, which is commonly called MCU. In this way, the configuration process is relatively easy. data transmission, storage, and reading are all performed on the master device. Update the entire update process as required, and reload the FPGA at the appropriate time. FPGA is almost completely isolated from the update process, so it is easy to meet the requirements.

Active updates are relatively cumbersome. First, flash may only have data interfaces on FPGA, indicating that flash reading and writing can only be initiated from FPGA. Second, because FPGA needs to Initiate flash update writing, therefore, it is also necessary to consider how FPGA obtains data. You can refer to the above description of the complete flash configuration update process. We can see that FPGA requires a data path (JTAG) to receive configuration data and implement a flash read/write controller to read and write flash. After flash is updated, the next configuration is triggered (re-powering ON/OFF) and the flash read operation is initiated to load the configuration data to complete the configuration.

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FPGA configuration method