FPGA frequency measurement principle and FPGA code

In general, there are two FPGA measurement frequency algorithms: frequency measurement and measurement Week. I used the electronic measurement textbook to find the definition. The frequency measurement is to count the input signal period within a certain period of time, while the measurement week is opposite. It is within the input signal period, count the standard signal period. It can be understood that the frequency measurement uses a slow clock to measure the high frequency, and the weekly measurement uses a fast clock to measure the low frequency cycle. This understanding is also in line with the "High Frequency frequency measurement, low frequency measurement Week" statement.

Take the frequency measurement algorithm as an example to write a program. The difficulty is to capture the gate start and end signs. Then we can use the time between the two rising edges of the low-frequency signal clock as the gate to count the input signal periods in the rising edges. Therefore, it is converted into capturing the clock signal edge. Generally, the capturing edge depends on the concatenation operator. Use {} and use & in VHDL &.

If posedge dataIn is used as a sensitive signal (because it is fast), when the rising edge of CLK is detected, the rising edge of dataIn is counted. When the next rising edge is reached, the output count is cleared.

Implementation Code:

Simulation results:

From the output result, there will be two count values (when division is not allowed). The difference between the two values is 1, which is acceptable. This Count value is sufficient in scenarios such as ask and PSK decoding. You only need to determine that the Count value is in the value range of + 1 or-1. If you want to test the actual frequency value, it is said that you have to calculate the Division using the formula fo = N/t. I have not tried it yet.

FPGA frequency measurement principle and FPGA code