FPGA Interview Guide

During this period, I interviewed several companies and found that large companies are focusing on basic issues. There are several other prominent issues here. They are: synchronous clock design, sub-steady state, asynchronous FIFO. It can be said that if these problems are identified, they will at least meet the technical requirements of 1/3. What is the other 2/3, I will not be clear. Some people have made a race risk glitch. However, for systems that adopt the synchronous design method, these problems are generally not encountered. Next, let's talk about my views on these issues. If you think that reading these things is similar to a bunch of shit, congratulations, your chance of a successful interview has increased by 1/3. If you think, what kind of cool people pulled a bunch of coops, so sorry, I 'd like to make up the course again. Here we recommend a book titled digital design-Principles and Practices (John F. Wakerly). Read it carefully. A synchronous clock is designed to trigger the same clock in a system (or a part of the system. All the (D) triggers in the system are connected to one clock, and only control the synchronization end of the trigger (input, synchronization slot, and Synchronous Reset ). Compared with asynchronous systems, asynchronous systems are not systems with different trigger clock ends connected to different clock signals (generally called cross-clock systems, is a combination of several smaller synchronization systems), but does not have the concept of clock, relying on the same feedback circuit as the trigger. Compared with asynchronous systems, synchronous systems are better designed (Asynchronous Design is like a magic, similar to the relationship between Assembly and advanced languages), and easier to perform Timing Analysis (Why D triggers instead of D latches) -- Here, the combination logic's Competitive Adventure glitch problem does not exist. It should be said that the biggest problem of the synchronization system is the skew of the clock (skew ). There are also some techniques involved in the synchronous clock system. These techniques generally focus on reducing the latency of key paths and balancing the time and space. These are balancing art (after understanding the basic components, the rest of the work is a word "balance"), the method here is too specific, and I do not know much about it, I dare not talk about it. However, if you have used one method, you can understand the spirit of it. This is the most basic problem in cross-clock design (the macro problem is FIFO). According to my observations, I usually don't understand this problem when I have asked many questions on the Forum. Please pay attention to it. What is a sub-steady state? A simple bi-stable circuit in a digital circuit is composed of two inverters connected at the beginning and end (some control logic is added to the latches and triggers). However, it is not shown by the name, this kind of circuit is actually in the third semi-stable State-that is, when both the inverters are in the middle, it is called the sub-steady state. We know that the feedback coefficient of the inverter in the range of non-logical values is quite large. Once the interference or noise leaves this center point, it will quickly enter the logical value range (steady state ). Mathematical Analysis enters the steady state from the sub-steady state. Just like the decay of radioactive elements, it is an exponential law (why is it an exponential law? If you don't understand it, it means you haven't understood the sub-steady state yet ). So what are the dangers of the Asian steady state? Power Consumption;), in fact, not (although the sub-steady state consumes a lot of power), the problem of the sub-steady state is that its level is not within the valid logical level range and is changing. This leads to different judgments (note, different) made by other digital components connected to them, some of which are regarded as '1', some as '0', and some of which are also in the sub-steady state, the digital components are logically disordered. So how can we avoid (or reduce) the danger of sub-steady state? Note that the probability of the sub-Steady-state trigger continuing to stay in the sub-steady state is reduced exponentially, so the method is to wait for a long enough time until the probability becomes small and will not actually happen. How long does it take? Some manufacturers have a data, and some do not, according to the common practice, at least wait for a clock cycle-this is the so-called asynchronous data should be hit with two triggers. This paragraph is a bit confused and not easy to explain. If you think the cloud is in the fog and yunyun, you have to find a book to learn. If you think the author cannot express it clearly, congratulations, the chance of passing the interview increases. There are many confused understandings about this issue. If your examiner disputes with you, you will follow his instructions. After all, no one wants to find a disciplined employee. Asynchronous FIFO is a concentrated embodiment of the Cross-Clock Domain Design Method, reflecting many methods. However, two of the most important points are the sub-steady state, and the other is the cross-clock transmission of multiple control/State signals, which is similar to but different from the sub-steady state. Specifically, when you transmit a set of signals to another clock domain, the signals may be delayed, so that they reach the new clock domain, the resulting data is different from the clock cycle of an old clock domain. Fortunately, for FIFO, a counter must be passed. This counter can be encoded as a gray code. This encoding only changes one bit at a time, it solves the problem above (if you haven't drawn any picture, you 'd better draw a picture to see it ). I don't know how this was invented! Note that there is also a requirement on the relative delay of the gray code and the related clock cycle. This is the most critical aspect of Asynchronous FIFO. It is easy to consider how to control pointers. Note that these things are not clear in your mouth. It is best to draw a picture. Don't let the examiner feel that you are not clear. Of course, there are many other things. For example, I have not studied the design skills of the combination logic. For example, the high-speed wiring signal integrity problem, I dare not say more. As for the design philosophy of the entire system, I dare not speak rashly. However, if you have a deep understanding of a problem, you can easily find out other problems.