Gains on the first day

I finally came to the place of study. I felt uneasy before I thought about it. But in order to pursue it, I also want to say something to myself. You must be brave enough to step out. A car at night can only light up 10 meters in front of the road, but it can also drive home, come on.

I talked about some syntaxes in the morning. It sounds a little relaxed for me, but I will also listen carefully and improve my knowledge. In the classroom, I interact with teachers and the students are very active, ask the teacher if you do not understand. Next, I will write down my notes for today.

1. Relationship between incentive documents and design documents

2. $ random is a 32-Bit Signed value, and {$ random} is a 32-bit unsigned value.

3. When declaring a port, if the port type is not declared, the system will define it as wire by default. Generally, the input port signal is defined as wire type, and the output port signal is defined as Reg type.

4. Always @ (B or D)

Begin

A = B;

C = D;

End

The signal on the right of the value assignment must appear in the sensitive signal list.

5. Always @ (posedge sclk) as long as it is triggered by the clock edge, all write non-blocking value assignment "<= ".

6. The essence of synthesis and unavailability lies in the ability to implement circuit-based non_syn: initial,

7. To prevent latches from being generated, you need to write the else and default statements.

Always @ (posedge sclk)

If () B <=;

Else B <=;

// Default: B <=;

8. Describe the finite state machine FSM with a unique heat code.

9. Comprehensive

-- Integrate wire variables into wire Variables

-- Reg variables may be integrated into wire, latches, and triggers.

10. How to assign an initial value to a variable

-- Reg [4: 0] A = 5' D2;

-- "If (! Rst_n) A <= 5'd2;

Gains on the first day