I2C bus occupied

Forward the blog about I2C by Mr. Netease DP, which is easy to find during learning.
Recently, it was found that the primary device reset may cause an I2C deadlock when accessing the I2C device. The result is high in the SCL and low in the SDA. After that, it is found that the I2C bus is pulled from the device. After the power is down from the device, SDA becomes high and becomes available after power-on

The message is normal. After that, SDA will automatically become a high level and the I2C bus will be restored by lowering the SCL signal line.
Under normal circumstances, the I2C bus protocol can ensure normal read/write operations on the bus. However, when the I2C main device is abnormally reset (the watchdog action, the Board power exception causes the reset chip action, manual button Reset

And so on) may lead to an I2C bus deadlock. The following describes in detail the cause of the bus deadlock.

In the process of reading and writing the I2C main device. after the start signal is sent, the main device controls the SCL to generate 8 clock pulses, and then lowers the SCL signal to a low level. At this time, the device outputs a response signal to convert the SDA

Signal pulling is low. If the primary device is abnormally reset at this time, the SCL will be released to a high level. At this time, if the device has not been reset, the I2C response will continue, and the SDA will be pulled to a low level until the SCL

To a low level, the response signal is terminated. For the I2C main device, check the SCL and SDA signals after resetting. If the SDA signal is found to be low, the I2C bus is considered to be in use and will be waiting for the SCL and SDA

The signal changes to high. In this way, the I2C master device waits for the SDA signal to be released from the device, while the I2C slave device waits for the master device to lower the SCL signal to release the response signal. The two wait for each other, and the I2C bus enters one person.

Deadlock status. Similarly, when I2C performs a read operation, I2C outputs data after the device responds. If the I2C master device resets abnormally at this time and the I2C data bit output from the device is exactly 0, it will also lead to I2C total

Line enters the deadlock status.

Method

(1) Try to use an I2C slave device with a reset device.

(2) connect all power supplies from I2C devices and connect them to the main power supply through MOS. The on-off of MOS is implemented by I2C Main devices.
(3) design the watchdog function on the I2C slave device.

(4) add I2C bus recovery to the I2C main deviceProgram.

After each I2C master device is reset, if the SDA data line is detected to be pulled low, the control of the SCL clock line in I2C generates 9 clock pulses (for 8-bit data, the "9 clks can be activated" method comes from NXP

As the originator of the I2C bus, NXP (Philips) is credible, so that I2C can complete the pending read operations from the device, recover from the deadlock status.

I2C bus deadlock causes and solutions-DP: the pace of life, progress...

This method has great limitations, because most of the main device's I2C module is implemented by the built-in hardware circuit, the software cannot directly control the display of the SCL signal to generate the clock pulse. Or, send

The i2c_stop condition can also allow the bus to be released from the device.

If the gpio is used to simulate the I2C bus implementation, before the I2C operation, add the I2C bus status detection i2c_probe. If the bus is occupied, you can try to recover the bus. After the bus is released, perform the operation again.

. It is necessary to ensure the integrity of the smallest unit of I2C operations and not be interrupted by other events (such as interruptions and high-priority threads.

(5) add an additional bus recovery device to the I2C bus. This device monitors the I2C bus. When the device detects that the SDA signal is pulled down for more than the specified time, nine clock pulses are generated on the SCL bus.

I2C reads the device and restores the deadlock. The bus recovery device must have a programming function. Generally, you can use a single-chip microcomputer or CPLD to implement this function.

(6) On I2C, a chain person has an I2C buffer with deadlock recovery. For example, linear's ltc1_7 is a bidirectional I2C bus buffer and has the I2C bus deadlock recovery function. Ltc12007 bus Transmission

The incoming side connects the main device, and the bus output side connects all slave devices. When ltc12007 detects that the SDA signal on the output side is dropped by 30 ms, the connection between the I2C bus input side and the output side is automatically disconnected.

16 clock pulses are generated on the SCL signal to release the bus. After the bus is restored, ltc00007 connects to the input and output sides again to enable the bus to work normally.