I2C Principles and Examples

	I2C bus principle and application example
	The I2C (Inter-Integrated Circuit) bus is a two-line serial bus developed by Philips to connect the microcontroller and its peripheral devices. The I2C bus was originally developed for audio and video devices in 1980s and is now mainly used in server management, including communication in the status of a single component. For example, the administrator can query each component to manage system configurations or master the functional status of the component, such as power supply and system fan. Multiple parameters such as memory, hard disk, network, and system temperature can be monitored at any time, which increases system security and facilitates management. 1 I2C bus featuresThe main advantage of I2C bus is its simplicity and effectiveness. Because the interface is directly on the component, the space occupied by the I2C bus is very small, which reduces the space of the circuit board and the number of chip pins, and reduces the interconnection cost. The bus can be up to 25 feet in length and support 40 components at a maximum transmission rate of 10 Kbps. Another advantage of the I2C bus is that it supports multimastering, in which any device capable of sending and receiving can become the master bus. A master can control signal transmission and clock frequency. Of course, there can only be one master at any time point.2 I2C bus working principle 2.1 bus composition and signal typeThe I2C bus is a serial bus consisting of the SDA data line and the clock SCL, which can send and receive data. Two-way transmission is performed between the CPU and the Controlled IC, and between the IC and IC. The maximum transmission rate is 100 kbps. Various controlled Circuits are connected in parallel on this bus, but just like telephones, only dialing their respective numbers can work. Therefore, each circuit and module has a unique address, in the process of information transmission, each module circuit connected to the I2C bus is both the master controller (or controller) and the transmitter (or receiver), depending on the functions it wants to accomplish. The control signal sent by the CPU is divided into address code and control amount. The address code is used for site selection, that is, the circuit to be controlled is connected to determine the type of control; the control value determines the type (such as contrast and brightness) of the adjustment and the amount to be adjusted. In this way, although each control circuit is mounted on the same bus, it is independent of each other and irrelevant to each other. The I2C bus has three types of signals during data transmission: start signal, end signal, and response signal. Start signal: in high-power mode, SDA switches from high level to low level to start transmitting data. End signal: When the SCL is low, the SDA is switched from low to high and the data is transmitted. Response signal: After receiving 8-bit data, the IC that receives the data sends a specific low-level pulse to the IC that sends the data, indicating that the data has been received. After the CPU sends a signal to the controlled unit, it waits for the controlled unit to send a response signal. After the CPU receives the response signal, it determines whether to continue to transmit the signal based on the actual situation. If no response signal is received, it is determined that the controlled unit has a fault. At present, many semiconductor integrated circuits have integrated I2C interfaces. Single-Chip Microcomputer with I2C interfaces include: cygnal's c8051f0xx series, philipsp87lpc7xx series, and microchip's pic16c6xx series. Many peripheral devices, such as memory and monitoring chips, also provide I2C interfaces.3. Basic bus operationsI2C procedures use Master/Slave bidirectional communication. When a device sends data to the bus, it is defined as a sender, and the device receives data as a receiver. Both the master and slave devices can work in the receiving and sending status. The bus must be controlled by the main device (usually a microcontroller). The main device generates a serial clock (SCL) to control the transmission direction of the bus and generates Start and Stop conditions. The data status on the SDA line can be changed only during the period when the SCL is low. During the period when the SCL is high, the SDA status change is used to indicate the start and stop conditions. See figure 1.
	Figure 1 Data Transmission sequence on the serial bus
	3.1 control bytesAfter the start condition, it must be the control byte of the device. The four-bit high is the device type identifier (the EEPROM is generally 1010 for different chip types ), the three digits are selected as slices, and the last digit is the read/write bit. When the value is 1, the read operation is performed, and when the value is 0, the write operation is performed. 2.
	Figure 2 control byte Configuration
	3.2 write operationsWrite operations are divided into two types: byte write and page write. page write operations vary depending on the bytes loaded at a time on the chip. For the address, response, and data transmission time series written on the page, see Figure 3.
	Figure 3 page write
	3.3 read OperationsThere are three basic read operations: Current address read, random read, and sequential read. Figure 4 shows the sequence of sequential reads. It should be noted that the 9th clock cycles of the last read operation are not "irrelevant ". To end the read operation, the host must issue a stop condition between 9th cycles or maintain SDA as high within 9th clock cycles, and then issue a stop condition.
	Figure 4 sequential read
	4 EXAMPLE: The realization of x24c04 and MCS-51 SCM Software and Hardware X24c04 is the CMOS 4096-bit serial EEPROM of Xicor, Which is internally organized into 512x8 bits. 16-byte page write. And MCS-51 MCU interface 5. Because SDA is an open-circuit output with a drain, it can be connected to any number of open-circuit or open-collector output "wire-or" (wire-ored. For more information about the pull-up resistance, see the x24c04 Data Manual. The following is a single-byte write operation routine for x24c04 through the I2C interface. The flowchart and Source Code are as follows:
	Figure 5 interfaces between x24c04 and 51 Single-Chip Microcomputer
	; Name: bsent; Description: Write byte; function: Write a byte ; Caller: none; input parameter: A; output parameter: None bsend: mov R2, #08 h; 1-byte 8-bit Senda: CLR p3.2; rlc; shifts one mov P3.3 and one C to the left; writes one SETB p3.2. Djnz R2, Senda; 8 bytes written? CLR p3.2; response signal SETB P3.3 SETB p3.2 RET
	Figure 6 Flowchart
	5 conclusionThe following points should be summarized in the application of I2C bus:: 1) perform operations in strict accordance with the sequence chart requirements, 2) If the interface is connected to a single-chip microcomputer interface with internal pull-up resistance, the pull-up resistance can be added. 3) in the program, The NOP command can be used to add a certain delay after the command operated on the counterpart line to match the corresponding transmission rate. 4) In order to reduce unexpected interference signals, you can use an external write protection pin (if any) to rewrite the data in the EEPROM, or write flags in space not used inside the EEPROM, perform a check at power-on or reset to determine whether the EEPROM is accidentally rewritten.
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I2C Principles and Examples