I2C protocol analysis

I. Technical Performance:
Serial 8-bit bidirectional data transmission bit rate up to 100 kbit/s in standard mode fast mode up to 400 kbit/s High Speed
Up to 3.4 Mbit/s;
Supports multi-host communication;
Multiple master control modules are supported, but only one master is allowed at a time;
A Serial Bus consisting of a data line SDA and a clock SCL;
Each circuit and module has a unique address;
Each device can use an independent power supply

Ii. basic working principle:
The start signal is used to take charge of the bus, and the stop signal is used to release the bus;
Each communication starts with start and ends with stop;
After the start signal is enabled, an address byte is sent, 7 of which are the address code of the controlled device, and 1 is the read/write control bit R/W, R. if the value of W is 0, data is written from the master to the controlled device. If the value of R/W is 1, data is read from the master to the controlled device;
When the controlled device detects that the received address is the same as its own address, it returns a response signal during the 9th clock period;
Each Data byte is before the transmission time (MSB;

Write communication process:
1. When the master node detects that the bus is idle, it first sends a start signal to manage the bus;
2. Send an address byte (including a 7-bit address code and a r/W );
3. When the controlled device detects that the address sent by the master device is the same as its own address, it sends a response signal (ACK );
4. After the master receives the ACK, it starts to send the first Data byte;
5. After receiving the Data byte, the controller sends an ACK to send the data. Sending Nack indicates that the data transmission is complete;
6. After the master sends complete data, a stop is sent to end the entire communication and release the bus;

Read communication process:
1. When the master node detects that the bus is idle, it first sends a start signal to manage the bus;
2. Send an address byte (including a 7-bit address code and a r/W );
3. When the controlled device detects that the address sent by the master device is the same as its own address, it sends a response signal (ACK );
4. After the master receives the ACK, it releases the data bus and begins to receive the first Data byte;
5. After receiving the data, the master sends an ACK message indicating that the data will be transmitted continuously. If the Nack message is sent, the data transmission is complete;
6. After the master sends complete data, a stop is sent to end the entire communication and release the bus;

Iv. Bus Signal Timing Analysis
1. Idle bus status
The two signal lines SDA and SCL are both at a high level, that is, all devices on the bus release the bus, and their respective pull-up resistors increase their levels;
2. Start Signal
The clock signal keeps the SCL high, and the SDA level of the data signal is lowered (that is, the negative hop is changed ). The start signal must be a hop-and-change signal, and the bus must be idle before the signal is established;
3. Stop the signal
The clock signal keeps the SCL high, and the data line is released, so that SDA returns the high level (I .e. positive hop). The stop signal must also be a hop signal.
4. Data Transmission
During the High-level period, the SDA line must maintain a stable level. The low level indicates 0 (at this time, the line voltage is the local voltage ), the high level indicates 1 (the voltage is determined by the VDD of the component ). The SDA level can be changed only when the SCL line is low.
5. Response Signal ACK
The I2C bus data is transmitted in bytes (8 bits). After each byte is sent, the device releases the data bus during the 9th pulses of the clock, the receiver sends an ACK (which lowers the power of the Data Bus) to indicate that the data is successfully received.
6. No response signal nack
The transmitter releases the data bus during the 9th pulses of the clock, and the receiver does not pull down the data bus to indicate an Nack, which has two purposes:
A. Generally, the receiver fails to receive data bytes;
B. when the receiver is the master controller and receives the last byte, it should send an Nack signal to notify the controlled transmitter to end data transmission and release the bus so that the master receiver can send a stop signal to stop.

5. Addressing conventions
There are two address allocation methods:
1. the IP address of a smart device with CPU is defined during software initialization, but cannot conflict with other devices;
2. Non-intelligent devices without CPU are solidified by the manufacturer inside the device and cannot be changed.

The 7-bit high is the address code, which is divided into two parts:
1. The 4-digit High is a fixed address that cannot be changed and is fixed by the manufacturer;
2. The low 3 position is the pin address, which can be set by the external pin (not all devices can be set );