Information Security System Design Foundation Fifth Week study summary

Processor architectureFirst, preface

1, computer system is limited to machine language program level.

2. The instruction is encoded as a binary format consisting of one or more byte sequences. The byte-level encoding of instructions and instructions supported by a processor is called its instruction set architecture (ISA).

3. Although the processor performance and complexity of each manufacturer is increasing, the different models are compatible at the ISA level. As a result, ISA provides a conceptual abstraction layer between compiler writers and processor designers, and compiler writers only need to know which instructions are allowed and how they are encoded. The processor designer must build the processor that executes the instructions.

4. The modern processor may actually work in a different way than the computational model implied by ISA. The ISA model should look like a sequential instruction execution, which is to take out an instruction and wait until it finishes executing before starting the next one.

5. Using caching in information retrieval data structures such as Web browsers or balanced binary trees and hash tables can improve performance while preserving the functionality of a simpler, more abstract model.

6. HCL: A simple language describing the control part of a hardware system that can be used to describe the processor design.

7. In this chapter, we define a simple and incomplete instruction set called the "Y86" instruction set. It is based on sequential operations, is functionally correct but is somewhat impractical. Because the processor performs a fully Y86 instruction per clock cycle, its clock must be slow enough to allow all actions to be completed within a cycle. We then create a pipelined processor that breaks down the execution of each instruction into five steps, each of which is handled by a separate piece of hardware or phase. Instructions step through each stage of the pipeline, and each clock cycle has a new instruction to enter the pipeline, so the processor can simultaneously execute the different stages of the five instructions. The processor is therefore required to handle many adventures or conflicts. Adventure is the location of an instruction or the operand depends on other instructions that are still in the pipeline.

ii. Y86 Instruction set architecture

Define an instruction set architecture that includes defining various state elements, instruction sets, and their encodings, a set of programming specifications, and exception event handling.

1, the programmer visible State

Programmer visible State: Each instruction in the program reads or modifies portions of the processor state.

The Y86 contains:

① Program Register:%EAX,%ECX,%EDX,%EBX,%ESI,%EDI,%ESP,%EBP. They can all store a word. %ESP is used as a stack pointer by the stack, stack, call, and return instructions.

②PC (program counter): Stores the address of the currently executing instruction. (in IA32, the address in memory that indicates the next instruction to be executed, denoted by%EIP.) ）
③ Program Memory: is a large byte array, saving the program and data. Y86 uses virtual addresses to refer to memory locations, and hardware and operating system software unite to translate virtual addresses into actual or physical addresses, indicating where the data is actually stored in memory.

④ Condition Code: ZF, OF, SF. is a conditional code used to hold information about the impact of the most recent arithmetic or logic directives.

⑤stat: The last part of the program state is the status code, which indicates the overall state of the program execution. It indicates whether a normal operation or an exception occurred.

2. Y86 directive

① in the MOVL directive, the first letter of the instruction name indicates the source type. The second letter of the instruction indicates the purpose type. Immediate count (i), register (R), memory (m). Memory references in two memory transfer instructions are simple base and offset forms. In address calculation, the scaling of the second and any register values is not supported. It is not allowed to transfer directly from one memory address to another, nor is it allowed to transfer the immediate number to memory.

The ②addl,subl,andl,xorl is a four integer operation instruction that only allows operation of the register data in the Y86 (also allowing operation of the memory data in the IA32), which sets the condition code ZF, SF, of.

③JMP,JLE,JL,JE,JNE,JGE,JG is a seven jump instruction that selects branches based on the type of branch instruction and the setting of the condition code.

The ④CMOVLE,CMOVL,CMOVE,CMOVNE,CMOVGE,CMOVG is a six conditional delivery instruction that has the same format as the Register-register transfer directive, but updates the value of the destination register only if the condition code satisfies the required constraint.

The ⑤call instruction returns the address to the stack and then jumps to the destination address. The RET instruction is returned from such a procedure call.

The ⑥PUSHL and POPL instructions are implemented into the stack and out of the stack.

The execution of the ⑦halt instruction stop instruction (instruction hlt in IA32). The application in IA32 does not allow this instruction because it causes the entire system to pause. For Y86, executing the halt instruction causes the processor to stop and set the status code to HLT.

3. Instruction Code

The byte-level encoding of the instruction is also visible in the ①. Each instruction requires a range of 1-6 bytes. The first byte of each instruction indicates the type of the instruction. This byte is divided into two parts, each part 4 bits: the height 4 bits is the code part, the low 4 bit is the function part. function values are only useful if a single set of related directives is shared with one code.

Each of the ②,8 program registers has a corresponding 0-7 register identifier, and the Y86 is identical to the register number of the IA32. The program register exists in a register file in the CPU, which is a small, random-access memory with the Register ID as the address. The ID value 0xF is used when it is necessary to indicate that no registers should be accessed.

The ③ has only one byte long because there may be a register designator byte attached , specifying one or two registers. These register fields are RA,RB. There are, none, no, only one will set the second to 0xF.

④ commands require an additional 4-byte constant number as the immediate number data or address indicator offset or branch instruction and the destination address of the calling instruction. All integers are encoded using a small-end method.

Note: The destination address of the branch instruction and the calling instruction is an absolute address, rather than using a PC-relative addressing method as in IA32. The processor uses a PC-relative addressing method, and the branch instruction is encoded more succinctly, which also allows the code to be copied from one part of the memory to another without having to update all the branch destination addresses.

For example:

An important property of the ⑤ instruction set is that byte encoding must have a unique interpretation. This property guarantees that the processor can execute the target code program without ambiguity. Even if the code is embedded in other bytes of the program, as long as the first byte of the sequence starts processing, we can still easily determine the sequence of instructions. Conversely, if you do not know the starting position of a code sequence, we cannot accurately determine how to divide the sequence into separate instructions.

Information Security System Design Foundation Fifth Week study summary