Instruction coding and decoding principles

Instruction sets are an important part of the processor architecture. The Instruction Set has two development aspects, including the CISC (Complex Instruction Set) represented by x86 and the Proteus (simplified instruction set) represented by arm and MIPS ). The goal of CISC is to use at least one or more commands to implement the functions that are frequently used as much as possible. Therefore, the running circuit of the command is often complicated, and the implementation of hardware functions is important; instead, it breaks down complex operating circuits, that is, it describes the function with as simple as possible multiple instructions, and reduces hardware complexity by using software, therefore, the requirements for the compiler are higher than those of the compiler. The command length of CISC is variable, and the running cycle is not fixed. The command length of the command is fixed, and the command length of the command is usually single-cycle. A large number of registers are also a feature of the Proteus.

This article focuses on the encoding and decoding of CPU commands, not just about the specific ratio of middleware-defined memory-to-memory and CISC. We all know that the CPU assembly line operation process includes finger fetch, decoding, running, memory and write-back (refer to blog: CPU command line operation ), however, many people only understand these steps in terms of concept. It is necessary to elaborate on these steps to understand the design and implementation of CPU commands.

We all know that C language is a highly abstract method for solving real problems and processes. Its Syntax mainly includes numerical values, logical operations, and branch control transfer. The numeric operation is addition, subtraction, multiplication, division, and division. The logical operation is the same as, or, non, XOR, and so on. The Branch Control Transfer includes the IF/else, for, while and other syntaxes. Assembly Language is a machine-level understanding and construction of C language. Its commands also contain numbers, logical operations, and branch control transfer. However, a single line of C language may require multiple Assembly commands for implementation. At the same time, because the commands are in the memory, and the CPU memory query register is much faster than the memory of the memory, the CPU operations are generally carried out in the registers, therefore, the assembly language generally needs to add memory and register direct data loading/storage commands. The CPU only recognizes binary input, so it can take the assembly language as a pseudo-code on the hardware layer, which is easy for developers to note, the same is a low-level language.

Instruction encoding is the process from an assembly language to a binary machine code. It is implemented by the assembler (the compiler converts the C language into an assembly language ). Now, if a simple CPU only supports four functions: including

1) Add Rd, RS, RN. The result is RD = Rs + rn.

2) subtract sub Rd, RS, Rn and the result is RD = RS-RN.

3) data transmission mov RD and Rs. The result is RD = Rs.

4) data is loaded into LDR Rd, [RS]. The structure is to assign the address value of the RS register in the memory to RD.

How to encode it?

1) First, the command is divided into two parts: the operation code and the operand. The operation code represents the command function, such as ADD and sub. It represents a specific circuit in the CPU, for example, add represents the addition circuit, sub represents the subtraction circuit, and the operand represents the input and output of the function, and the input and output of the corresponding circuit.

2) currently there are four functions in common, so at least two bits are required for encoding. For example, 00 represents add, 01 represents sub, 10 represents mov, and 11 represents LDR;

3) The operands are encoded. If there are eight registers, the RD, RS, and Rn are all one of them, that is, the range of D, S, and N is 0 to 7, it requires at least three bits for encoding. For example, 000 represents r0, 001 represents R1, and so on. 111 represents r7.

To implement the above four functional commands, a total of 2 + 3 + 3 + 3 = 11 bits are required for encoding. For example, sub R6, R1, R2, that is, R1 minus R2 value is assigned to R7, And the encoding is 01 110 001 010.

After understanding the instruction encoding, the Instruction Decoding should be better understood than the encoding. According to the current program count register PC (if the hardware circuit requires R7 is the register PC) value from the memory machine code command, the value of this machine code is 01 110 001 010. The next process is decoding, which is sent to the decoder based on the first two bits 01. The decoder is a subtraction circuit. The decoder is 110, which is R6, And the decoder 001 is R1, 010 select R2. for decoding and then run the command. Run the subtraction unit circuit to calculate the two inputs (R1, R2) and assign the result to r6.

The read/write operations and decoding operations are completed by the CPU control unit (Cu). The operation is completed by the ALU (logical operation unit). It can be seen that ALU is a collection of many types of circuits. The Design of CPU commands is closely related to the instruction code.

The arm and MIPS CPUs are both 32-bit characters long, so the instruction code is 32 bits, which can support and express many other functions (operation codes) and registers (operands ). For example, the arm system is R0 to R15, so four bits are required to represent it. Of course, the arm register also has the concept of a group, that is, the registers that the CPU may see in different working modes may be different, such as R13 and R14. During decoding, not only the instruction operand must be used as the input, but also the value of the Current Status Register must be used as the input.

What is the reason for the 16-bit instruction set? Because of the same piece of C code, coding with 16-bit instructions can save 30% of the Code compared with 32-bit encoding. The less code, the less memory occupied, the lower the natural cost. In the MCU field, it is generally cost-sensitive, so 16 is widely used in the MCU field.

The Instruction Design of arm and MIPs is based on 32-bit, and its operation is also 32-bit. How can we implement 16-bit instruction sets in a 32-bit instruction set? We all know the 20% principle, that is, 80% of the instruction usage will reach 20%, So we encode the instruction (which is a subset of the 32-bit instruction, naturally, we can use a small number of BITs for encoding. When using 16-bit commands, we can force them to use only a part of registers, it is natural that registers can be encoded with fewer bits. The 16-bit instruction set can be considered as a subset of the 32-bit instruction set. In the decoding phase, the CPU converts 16-bit instructions into 32-bit instructions, and then performs decoding and running.

Arm's 16-bit instruction set is the thumb instruction set, and MIPS's 16 is the mips16 instruction set. For the seamless switch between the 32-bit Instruction Set and the 16-bit instruction set, refer to another blog article: the active switch mechanism of the 32-bit and 16-bit instruction sets mode.

Instruction coding and decoding principles