ISE pin constraint setting parameter details

In Ise, the set pin can be constrained by opening the Assign package pins in user constraints.

Xilinx pack-[design Object list-i/o Pin opened]

Where the parameters are set as follows

I/O name--io pin name, corresponding to the input and output pins in module.

I/O Direction--Sets the input or output pin.

Loc-Located on the chip.

Bank-the bank block where the pin is located, and when LOC is specified, the bank is determined.

FROM:SPARTAN-3E FPGA series Data Sheet P19

I/O Std. Level standard for--i/o pins.

Each bank can be arbitrarily set to the level standard supported by the device, different level standards in a bank to be aware of their level to be consistent, such as 3.3v, level can be Lvttl, LVCOMS33.

FROM:SPARTAN-3E FPGA series Data Sheet p16~17

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Here's a look at common logic level standards

The

Now commonly used level standards are TTL, CMOS, LVTTL, LVCMOS, ECL, PECL, LVPECL, RS232, RS485, and some faster than the high  lvds, GTL, Pgtl, CML, Hstl, Sstl and so on. The following is a brief introduction to the respective power supply, level standards and precautions to use. The

Ttl:transistor-transistor logic  transistor structure.
vcc:5v;voh>=2.4v;vol<=0.5v;vih>=2v;vil<=0.8v.
because there is a great deal of idle between 2.4V and 5V, there is little benefit in improving the noise tolerance, and it will increase the power consumption of the system and also affect the speed. So I cut off a part of it later. That's the back of the Lvttl. The
Lvttl is also Lvttl (Low Voltage TTL) of 3.3V, 2.5V, and lower voltages.

3.3V LVTTL:
vcc:3.3v;voh>=2.4v;vol<=0.4v;vih>=2v;vil<=0.8v.

2.5V LVTTL:
vcc:2.5v;voh>=2.0v;vol<=0.2v;vih>=1.7v;vil<=0.7v. The
Lower Lvttl is not used first. Multi-use in the processor and other high-speed chips, when used to view the chip manual is OK.

TTL usage Note:

TTL level general overshoot will be more serious, may be at the beginning of the string 22 ohms or 33 ohms, TTL level input pin is internally considered high level. To drop the words apply 1k below the resistor drop down. The TTL output does not drive the CMOS input.

Cmos:complementary Metal Oxide Semiconductor?? Pmos+nmos.
vcc:5v;voh>=4.45v;vol<=0.5v;vih>=3.5v;vil<=1.5v.
The relative TTL has a greater noise tolerance, and the input impedance is much larger than the TTL input impedance. corresponding to the 3.3V LVTTL, there is a lvcmos, which can be directly driven with the LVTTL of 3.3V.

3.3V LVCMOS:
vcc:3.3v;voh>=3.2v;vol<=0.1v;vih>=2.0v;vil<=0.7v.

2.5V LVCMOS:
vcc:2.5v;voh>=2v;vol<=0.1v;vih>=1.7v;vil<=0.7v.

CMOS Use NOTE:

The CMOS structure has a controllable silicon structure inside, and when the input or input pins are higher than a certain value of VCC (for example, some chips are 0.7V), the current is large enough to cause latch-up effect, causing the chip to burn.

Ecl:emitter coupled logic emitter-coupled logical circuit (differential structure)
vcc=0v;vee:-5.2v;voh=-0.88v;vol=-1.72v;vih=-1.24v;vil=-1.36v.
The speed is fast, the driving ability is strong, the noise is small, it is easy to reach hundreds of m application. However, the power consumption is large and negative power is required. To simplify the power supply, there was a pecl (ECL structure, switched to positive voltage) and lvpecl.
Pecl:pseudo/positive ECL
vcc=5v;voh=4.12v;vol=3.28v;vih=3.78v;vil=3.64v
Lvpelc:low Voltage PECL
vcc=3.3v;voh=2.42v;vol=1.58v;vih=2.06v;vil=1.94v

ECL, PECL, lvpecl use note:

Different levels cannot be driven directly. AC-coupled, resistor networks or special-purpose chips can be used in the intermediate conversion. All of the above three are shot with the output structure, must have a resistor pulled to a DC bias voltage. (such as multi-lvpecl for clocks: DC matching with 130 euro pull-up, while using 82 euro pull, ac matching with 82 euro pull, while using 130 euro drop.) But the two ways to work after the DC ping du at about 1.95V. )

The front level standard swing is relatively large, in order to reduce electromagnetic radiation, while improving the switching speed and the introduction of LVDS level standards.
Lvds:low Voltage Differential Signaling
Differential pair input and output, there is a constant current source 3.5-4ma, change the direction on the differential line to represent 0 and 1. The differential level of the ±350mv is converted to an external 100-Ohm matching resistor (and close to the receiving end on the differential line).

LVDS Use Note:

Can reach more than 600M, PCB requirements are high, differential line requirements are strict and so on, preferably not more than 10mil (0.25mm). 100 ohms distance from the receiving end can not exceed 500mil, preferably controlled within 300mil.
The following level may not be a lot, the length of the relationship, just a brief introduction. If you are interested, you can contact me.

CML: A circuit that is well matched internally and does not need to be matched. Transistor structure, is also a differential line, the speed can reach more than 3G. Only point-to-point transmission.

GTL: A CMOS-like structure, the input is the comparator structure, the comparator one end of the reference level, the other end of the input signal. 1.2V power supply.
vcc=1.2v;voh>=1.1v;vol<=0.4v;vih>=0.85v;vil<=0.75v
pgtl/gtl+:
vcc=1.5v;voh>=1.4v;vol<=0.46v;vih>=1.2v;vil<=0.8v

Hstl is a level standard used primarily for QDR memory: generally v&not; ccio=1.8v and v&not;&not; Ccio= 1.5V. Similar to the above GTL, the input is the comparator structure, the comparator is connected to the reference level (VCCIO/2), and the other end is connected to the input signal. The reference level requirements are relatively high (1% accuracy).

The SSTL is primarily used for DDR memory. and Hstl basically the same. v&not;&not; CCIO=2.5V, the input is the comparator structure, the comparator is connected to the reference level 1.25V, and the other end is connected to the input signal. The reference level requirements are relatively high (1% accuracy).
Hstl and SSTL are mostly used below 300M.

RS232 and RS485 Basic and everyone more familiar, only briefly mention:
RS232 uses ±12-15v power supply, the serial port behind our computer is the RS232 standard. +12V indicates that 0,-12V represents 1. Can be converted with a special chip such as MAX3232, or you can use two transistors plus some peripheral circuits for inverting and voltage matching.

The RS485 is a differential structure with a higher anti-jamming capability relative to the RS232. Transmission distances up to thousands of meters

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Drive Str. The drive current of the--i/o pin.

The relationship between the logic level size and the output current intensity size:

FROM:SPARTAN-3E FPGA series Data Sheet P19

termination-terminal structure (resistor pull-up/resistance drop/float).

Pulldown and Pullup Primitives

There are three types of digital circuits: high, low, and higher impedance. Some applications do not want a high-impedance state, which can be stabilized by a pull-up resistor or a pull-down resistor, as shown in the figure. The I/O port of the FPGA can be pulled up or down through the external resistor, or inside the chip, through configuration.

The pull-up resistor is used to provide current when the bus drive capacity is insufficient;

And the pull-down resistor is used to absorb the current;

Through the FPGA internal configuration to complete the upper and lower pull, can effectively save the board area, is the design of the preferred solution.

Schematic diagram of the upper and lower pull circuits

The primitives of the upper and lower drop are pullup and pulldown respectively.

1) example code for Pullup primitives

Pullup: Pull-up primitives (I/O Buffer Weak pull-up)

Applicable chip: All chips

Xilinx HDL Library Wizard version, ISE 9.1

Pullup Pullup_inst (

. O (o),

Pull-up outputs, which need to be directly connected to the design's top-level module ports);

To end the Pullup process of the module

2) example code for Pulldown primitives

PULLDOWN: Drop-down primitive (I/O Buffer Weak pull-down)

Applicable chip: All chips

Xilinx HDL Library Wizard version, ISE 9.1

PULLDOWN Pulldown_inst (

. O (o),

Drop-down output, requires direct connection to the design's top-level module port

);

To end the pulldown process of the module

(FROM:FPGA Development Practical Tutorial Section 4th how to use Xilinx corporate primitives

http://www.eefocus.com/article/08-03/37457s.html)

FROM:SPARTAN-3E FPGA series Data Sheet P18

When the option Keeper (dangling) is selected, the bus is suspended without driving current, and all the drives are flipped to maintain a logic level.

Slew--slew rate. The rate at which the signal is converted can be understood as the slope of the signal at a certain point.

It is not only for the clock signal, such as the amplifier's slew rate is a very important parameter, but in the digital circuit, it may be more often used to describe the chip input signal changes.

In Xilinx's design environment, the slew rate of the output signal can be set to fast or slow. When set to fast, the slope of the signal change is improved, which increases the rate of signal conversion, but also increases the ringing of the pulse signal. Therefore, do not set the slew rate of the output signal to fast unless it is a last resort.

Skew-Fast,io conversion is fast, but large current, power consumption.
Skew Slow,io conversion is slow but consumes less power. ^: Y! p:v/w* ~ "o$ h
See the DC AC switching feature manual for the device for detailed instructions.

Default settings

Iostandard=lvcmos25

Slew=slow

Drive=12

delay--input delay. Adding delay can slow down the ascent speed. BOTH, Ibuf, IFD, none of these four alternatives

Ifd--registered Inputs

Programmable mixed input delay unit:

FROM:SPARTAN-3E FPGA series Data Sheet P12

Diff. Type

Resources:

1) difference between Lvttl and Lvcmos

http://nylzhaowei.blog.163.com/blog/static/14303922007324104723589

2) Practical tutorial for FPGA Development Section 4th how Xilinx uses the original language of the company

Http://www.eefocus.com/article/08-03/37457s.html

3) Riple ' s Blog:stay hungry. Stay foolish.

An example of FPGA timing problem--electromagnetic interference and pin-driven current constraints

This article describes the relationship between the choice of slew rate and EMI

4) Standard level definition for several interfaces

Http://bbs.weeqoo.com/bbsdetail-32425-8.html

5) Electronic Engineering album website Forum PCB Design Technology Question and answer essence (2)-EMI/EMC design

Http://www.pcbfans.cn/article/3d/5390$2.html

6) How Xilinx FPGAs use LVDS http://www.61eda.com/Services/help/Xilinx/200803/1225.html Tags: