LCD Drive learning notes (2) [model: spfd5408]

At the beginning, I thought it was a common practice to use gpio to drive the LCD. But it is different. This time, the FPGA board is used to drive the LCD. I checked some information. This method is similar to FSMA driving LCD.
For MCU Bus, LCD has only two addresses, corresponding to rs = 0 and rs = 1 respectively.
1. Write commands with RS = 0
2. rs = 1 Write Data
Write_reg is divided into two steps: write command (Register address); write data (register data)
Read_reg two-step paging: write command (Register address); read data (register data)
All register addresses, register data, and Gram data are transmitted through data lines, rather than the SRAM address. this is easy to confuse. the LCD has only one SRAM address, which is Rs.
Because we use SRAM to drive the LCD, the time sequence is automatically completed by MCU. At the beginning, I did not understand the meaning of "automatic". Later I checked some information and understood a little.
Read Memory is generally used by the SRAM controller to enable chip selection of CS. The address output on the address bus is RD = 0, wR = 1, and the memory then responds to these signals and Outputs Data on the Data Bus, the SRAM then reads the data on the Data Bus.
Write memory is generally used by the SRAM controller to enable chip selection of CS. The address is output on the address bus and the data is output on the Data Bus. RD = 1, wR = 0, the memory then responds to these signals and writes the data on the data bus to the internal storage unit.
# Define sram_ LCD _data (uint32_t) 0x60020000) // disp data ADDR
# Define sram_ LCD _cmd (uint32_t) 0x60000000) // disp Reg ADDR
// Write Register address Function
Void LCD _wr_reg (unsigned int index)
{
* (Volatile uint16_t *) (sram_ LCD _cmd) = index;
}
// Write register data Functions
Void LCD _wr_cmd (unsigned int index, unsigned int Val)
{
* (Volatile uint16_t *) (sram_ LCD _cmd) = index;
* (Volatile uint16_t *) (sram_ LCD _data) = val;
}
Sram_ LCD _cmd is the write register. At this time, RS = 0, which tells the LCD that the data I output on the bus is the register address.
Sram_ LCD _data is the write data. At this time, RS = 1 tells the LCD that the output data on the bus is the register data or gram data.
Next, let's talk about how to determine the addresses of sram_ LCD _cmd and sram_ LCD _data.
First, sram_ LCD _cmd. This depends on the SRAM chip connected to the CS pin of the LCD and determines the base address.
Sram_ LCD _data is based on the address line from the LCD rs to the SRAM. Another point is the screen data type.
For 8-bit data, if RS is connected to A0, sram_ LCD _data = sram_ LCD _cmd + 1. Sram_ LCD _data = sram_ LCD _cmd | 1 <n

If the data type is 16bit. 1 In the address line corresponds to 2 bytes in the base address. Sram_ LCD _data = sram_ LCD _cmd | (1 <n) * 2

The LCD screen can be cleared. Let's talk about debugging problems. As the company is developing chips, I am running programs on FPGA boards.

SRAM----------------------------LCD

CE--------------------------------CS

A [0: 24] --------------------------- rs

Data--Data Cable

OE--------------------------------RD

WE-------------------------------WR

Reset---Reset

The corresponding PIN is similar to this. The LCD model I used is spfd5408. From datasheet,

1,

The RST pin needs to be pulled down for at least 1 ms before being pulled up. This means that the reset needs to be connected to the reset key of the Board.

2. The data type of the LCD screen is 16 bits. Paste the image above,

This table indicates that when a 16-bit data-width external memory is used, the internal haddr [25] is shifted to the external bus A24 ~ Internal haddr [0] is not output on A0.

A0 is not connected, so the A1 on the sram is equivalent to A2, 1 <n ----> 1 <(n + 1)