The Amba LCD controller of the Linux kernel uses the Clcd_panel structure to represent the hardware parameters of an LCD screen:
[CPP] View plain copy/* include/linux/fb.h */ struct fb_videomode { const char *name; /* optional */ u32 refresh; /* optional */ u32 xres; u32 yres; u32 pixclock; u32 left_margin; u32 right_margin; u32 upper_margin; u32 lower_margin; u32 hsync_len; u32 vsync_len; u32 sync; u32 vmode; u32 flag; }; /* include/linux/amba/clcd.h */ struct clcd_panel { struct fb_videomode mode; signed short width; /* width in mm */ signed short height; /* height in mm */ u32 tim2; u32 tim3; U32 cntl; unsigned int bpp:8, fixedtimings:1, grayscale:1; unsigned int connector; };
Let's look at an example: http://lxr.linux.no/linux+v2.6.37.4/arch/arm/mach-lpc32xx/phy3250.c
Fb_videomode the meaning of each parameter Linux's abstraction of the LCD is shown in the following figure:
Here's a look at what each member of Fb_videomode means:
| Name |
Abbreviations in the data sheet |
Chinese name |
Significance |
Note |
| Name |
No |
Name |
LCD name (optional) |
No |
| Refresh |
No |
Refresh Rate |
Refresh rate (many examples in the kernel are assigned a value of 60) |
No |
| Xres |
No |
Line width |
Number of pixels per row |
No |
| Yres |
No |
Screen height |
Number of lines on the screen |
No |
| Pixclock |
No |
Pixel clock |
The length of the clock cycle for each pixel, in units of picosecond (10 minus 12 squared per 1 seconds) |
No |
| Left_margin |
HBP (horizontal back Porch) |
Horizontal Rear Edge |
The image to be inserted when the pixel data of each row or column begins to output
Number of vegetarian clock cycles |
No |
| Right_margin |
HFP (horizontal Front Porch) |
Horizontal Frontier |
End of pixel at each row or column to the LCD line clock output pulse
The number of pixel clocks between |
No |
| Upper_margin |
VBP (Vertical back Porch) |
Vertical Back Edge |
Invalid number of lines at the beginning of a frame after a vertical synchronization cycle |
No |
| Lower_margin |
VFP (Vertical Front Porch) |
Vertical Frontier |
End of this frame data output to the beginning of the next frame vertical synchronization cycle
Number of invalid rows before |
No |
| Hsync_len |
HPW (HSYNC plus width) |
Line synchronization Pulse width |
Units: Pixel clock cycles |
There are also manuals for short HWH (HSYNC width) |
| Vsync_len |
VPW (VSYNC width) |
Vertical Sync pulse Width |
Units: Displays a row of time th |
There are also manuals for short vwh (VSYNC width) |
| Sync |
No |
Sync polarity Setting |
Fb_sync_hor_high_act can be set as needed (horizontal sync high Active) and fb_sync_vert_high_act (vertical sync high Active) |
No |
| Vmode |
No |
No |
Most of the samples in the kernel are directly set to fb_vmode_noninterlaced. Interlaced means interlaced [interlaced] scanning, the TV uses 2:1 interleaving rate, that is, two fields per frame, vertical scan two times, one scan odd lines, and another scan even rows. It is clear that LCD is not currently in this mode. |
No |
| Flag |
No |
No |
No usage is currently seen |
No |
Note: (1) The abstraction of the Linux LCD is image-centric, while the LCD manual is centered on the synchronization signal, so the left_margin in the kernel refers to the number of idle cycles before each line (the front is naturally the left), and it corresponds to the horizontal back edge of the LCD data sheet (HBP Horizontal back Porch), refers to the idle period after the line synchronization signal. The reference is different, but the same thing is said. (2) The horizontal synchronous signal is sometimes also the line synchronous model, the vertical synchronization signal is called the field synchronization signal. (3) for the Frambuffer abstract model of LCD, refer to the documentation in the kernel: documention/fb/frambuffer.txt. (4) The usefulness of Fb_videomode members is my own reference to the kernel code in the Include/linux/amba/clcd.h in the Clcdfb_decode () function summarized, does not guarantee that the protection is absolutely correct.
The meaning of each member of the Clcd_panel Clcd_panel is the proprietary data structure of the AMBA LCD controller of ARM, defined in the include/linux/amba/clcd.h. ARM's AMBA LCD Controller data Sheet is here: http://infocenter.arm.com/help/topic/com.arm.doc.ddi0121d/DDI0121.pdf width and height units are in mm, It should refer to the physical size of the screen. But in the DRIVERS/VIDEO/AMBA-CLCD.C is simply assigned to Fb.var.width/height, most of the kernel examples are directly assigned to-1.
TIM2 is the clock and signal polarity register from the Clcdfb_decode () function in Include/linux/amba/clcd.h and the Clcdfb_set_par () function in DRIVERS/VIDEO/AMBA-CLCD.C , the TIM3 is an end-of-line control register that controls whether a pulse is output after each line of output. TIM3 general, use default values. TIM2 generally according to the LCD data sheet with the following several macro assignment: #define TIM2_CLKSEL (1 << 5) Select the LCD clock source, 0 Select the on-chip clock, 1 Select the external pin access clock. Typically, you can use the default value
#define TIM2_IVS (1 << 11) Reverses the polarity of the vertical sync signal. 0: Active high, low level invalid. 1: On the contrary
#define TIM2_IHS (1 << 12) Reverses the polarity of the horizontal sync signal. 0: Active high, low level invalid. 1: On the contrary
#define TIM2_IPC (1 << 13) to select whether the pixel data is driven to the LCD data cable at the rising or falling edge of the display clock. 0: Rising edge. 1: Falling Edge.
#define TIM2_IOE (1 << 14) This bit selects the effective polarity of the output enable signal. 0: Active high, low level invalid. 1: On the contrary
#define TIM2_BCD (1 << 26) Set this bit to 1, which invalidates the frequency division of the PCD. Mainly used for TFT display. This bit is not usually set, using the default value of 0.
The CNTL member of the Clcd_panel is actually the control register to write to the Amba LCD controller, populated with the following macro based on the specific hardware: #define Cntl_lcden (1 << 0) LCD enable control bit. 0: Forbidden. 1: Enable.
#define CNTL_LCDBPP1 (0 << 1) bit[1-3] defines the color depth. Bpp:bits per pixel, the number of bits per pixel. = 1 BPP. #define CNTL_LCDBPP2 (1 << 1) 001 = 2 BPP.
#define CNTL_LCDBPP4 (2 << 1) 010 = 4 BPP.
#define CNTL_LCDBPP8 (3 << 1) 011 = 8 BPP.
#define CNTL_LCDBPP16 (4 << 1) = + BPP
#define CNTL_LCDBPP16_565 (6 << 1) (+ BPP), 5:6:5 mode
#define CNTL_LCDBPP24 (5 << 1) 101 = the BPP (TFT panel only).
#define CNTL_LCDBW (1 << 4) STN LCD monochrome/color selection. 1: Color, 0: Monochrome
#define CNTL_LCDTFT (1 << 5) LCD display TFT type selection. 0:STN display, using a gray scale calibration device. 1:TFT display, do not use the gray scale calibration device
#define CNTL_LCDMONO8 (1 << 6) This bit determines whether a monochrome STN LCD uses a 4-bit parallel interface or a 8-bit parallel interface. 0:4-bit interface.
#define CNTL_LCDDUAL (1 << 7) STN single LCD display or dual LCD display selection. 0= Single
#define CNTL_BGR (1 << 8) Color mode selection, 0=rgb: normal output, 1=BGR: Red and blue swap locations
#define CNTL_BEBO (1 << 9) controls the storage order of bytes in memory: 0= byte order, 1 = big endian byte order
#define CNTL_BEPO (1 << 10) to set the way of pixel sorting, 0= using small-end pixel sorting, 1= using big-endian pixel sort
#define CNTL_LCDPWR (1 <<) LCD power Enable. 1=LCD display power on and lcdv[23:0] signal enable
#define CNTL_LCDVCOMP (x) ((x) <<) LCD is interrupted vertically. 00= Vertical sync pulse is active, 01 = vertical back edge, 10 = Active video image start, 11 = vertical Front Start
#define CNTL_LDMAFIFOTIME (1 <<) DMA FIFO request delay
#define Cntl_watermark (1 <<) LCD DMA FIFO watermark. 0: Generates an LCD DMA request when the DMA FIFO contains 4 or more empty cells. 1:8.
cntl_lcdbpp16_565, Cntl_lcdtft, CNTL_BGR, Cntl_lcdvcomp (x) are generally initialized. Cntl_lcden and CNTL_LCDPWR will be driven to automatically set the position. Cntl_lcdvcomp (x) is generally initialized to Cntl_lcdvcomp (1) .<
