From: http://hi.baidu.com/huyudu
After being set to the receiving mode, the nrf24l01 can receive data through six different data channels (data pipe.
Each data channel has a unique address, but the frequency of each data channel is the same. This means that there can be six nrf24l01 configured as the sending status, which can communicate with the nrf24l01 configured as the receiving status, in addition, the receiver can be differentiated (by determining the 1-3 bits of the Status Register ).
Data Channel 0 has a unique 40-bit configurable address. For other channels, the first 32 bits are the same, and the last 8 bits are different. All data channels can implement the enhanced shockburst mode.
On the sender side, Data Channel 0 is used to receive confirmation information. Therefore, the address of Data Channel 0 on the sender must be the same as the sending Address to receive the response information.
After a 24l01 message is sent, it opens the receiver and waits for confirmation. If no confirmation is received, resend until confirmation is received. When the resend exceeds a certain number of times, the interrupt is triggered and the Status Register is changed. The limit on the number of resends is set in the setup_retr_arc register.
Whenever a confirmation is received, the previous packet is considered to have been successfully sent. This packet will be cleared from the sending buffer and tx_ds IRQ will be set to high.
Each time the SPI write is started, status words are read back.
Enhanced shockburst package format
Pre-domain 1 byte
Address Field 3-5 bytes
Package control domain 9bit
Load 0-32 bytes
Bytes of CRC1-2
The address field is the receiver address.
Package control domain
Load Length: 6 bits
Pid2bit
No_ack1bit
Load Length: 6 bits indicates a maximum of 32 bytes
PID: Used for the package number to determine whether it is a resend package or a new package
No_ack: Indicates whether to automatically respond. If it is set to 1, no automatic response is required.
The latency and retransmission times of automatic responses are programmable.
The relationship between the 24l01 operating mode and registers and IO ports is as follows:
Functions of Ce pins
An ESB (enhanced shockburst) sends one byte and receives ack about 339us.
From the powerdown status, you must first enter the standyby status. This status conversion requires MS latency, and from the standyby status to the Rx/TX status, you need 130us
Set the high CE to maintain at least 10 US, and enhanced shockburst is enabled.
Enhanced shockburst Mode
1. Configure the config register and set prim_rx to 0, indicating the sending mode.
2. When sending data, you must first configure the tx_addr address. This address should be the acceptor address (that is, one of the six data pipe addresses at the acceptor can ensure that the recipient receives the data ). If you want to use automatic response, because the response message is received by the sender's datapipe0, the address of the sent datapipe0 should be the same as tx_addr (if it is the same address as the previous one, you do not need to rewrite the address ).
3. Configure the data Load Length tx_pld and send the data to be sent to nrf24l01. When the data load is continuously written through SPI, nrf24l01 will automatically count the number of bytes. (The data load must be continuously written when CS is low)
4. Set ce to high and maintain at least 10 us. This pulse will start sending shockburst
5. nrf24l01:
A) Enable RF
B) Start the crystal oscillator.
C) data packaging
D) send data
6. If an automatic response is started (and the number of retransmissions does not reach the maximum value), nrf24l01 is automatically transferred to the receiving status.
1: If a response packet is received within the specified time, this is a successful sending. The data in the Tx FIFO is cleared and the tx_ds bit in the Status Register is set to higher.
2: automatic retransmission if the response packet is not received within the specified time period (when automatic re-transmission is enabled, the number of retransmissions is specified by the arc bit in the setup_retr register ).
3: When the number of retransmissions reaches the maximum value, the response is still not received, the max_rt in the Status Register is set to high, and the data in the Tx FIFO buffer is not removed.
If the value of max_rt or tx_ds is set to a high value, it will interrupt the IRQ pin (the low level is valid, and the corresponding bit in the rewrite Status Register can be cleared ). No data can be sent before max_rt is cleared after max_rt reaches the maximum retransmission count and causes interruption. Each time max_rt is interrupted, the plos_cnt counter will add 1 to count the number of packet loss.
7. After the CE is set to low, the device enters the standby_ I status. Otherwise, the next data load in the Tx FIFO buffer will be sent. If the data buffer is empty and CE is still high, the device enters STANDBY-II mode.
8. If the device is in STANDBY-II mode, the device enters STANDBY-I mode When CE is low.
(Standby mode can reduce current consumption. In this mode, SPI communication can still be completed)
Data receiving process in enhanced shockburst Mode
1. Set prim_rx In the config register to 1 and set ce to high.
After 2.130us, nrf24l01 began to monitor RF Signals
3. when valid packets are received (address matching), the data is stored in the RX-FIFO buffer, the rx_dr in the Status Register is set to high, and the IRQ pin sends an interrupt signal at the same time (if this signal is not blocked ). The rx_p_no in the Status Register indicates the data pipe number that should receive the data.
4. If automatic response is enabled, a response signal will be sent
5. MCU sets ce to low to enter STANDBY-I Mode
6. MCU can read the received data through SPI
Note the following points about the 24l01 networking:
(1) Pay attention to Address Allocation
The document clearly states that only channel 0 has a configurable address of 5 bytes, and the other five nodes only have 1 byte of free configuration address,
For example, you can configure uint const rxadr0 [rx_adr_width] = {0x34,0x43,0x10,0x10,0x01} on the receiving node. // The Receiving address
Uint const rxadr1 [rx_adr_width] = {0xc2, 0xc2, 0xc2, 0xc2, 0xc1}; // Channel 1 Address
Uint const rxadr2 [1] = {0xc2}; // Channel 2 address
Uint const rxadr3 [1] = {0xc3}; // Channel 3 address
Uint const rxadr4 [1] = {0xc4}; // Channel 4 address
Uint const rxadr5 [1] = {0xc5}; // Channel 5 address
Then, set the sending node address and the corresponding channel address at the acceptor to be the same.
(2) the receiving node distinguishes the sending nodes.
This is the purpose of distinguishing between 1-3 bits in the Status Register.