PIC Analysis of Programmable Interrupt Controller of or1200 Processor

The following is an excerpt from the book "Step by Step surprise core-software core processor internal design analysis ".

16.3 Programmable Interrupt Controller PIC analysis 16.3.1 PIC Introduction

Programmable Interrupt Controller (PIC) is used to respond to various interrupt events, such as Keyboard Events and arrival of serial data. PIC collects all interruptions and notifies the arrival of CPU interruptions, the latter is transferred to the interrupt processing routine for processing. Or1200 supports up to 32 interruptions. Its function mainly relies on two special registers: the interrupt shielding register picmr and the interrupt Status Register picsr. You can use picmr to determine whether to block certain interruptions. You can use picsr to know the information of the interrupt source. Picmr and picsr are 9th special registers, as shown in Table 16.7.

The format of the interrupt shield register picmr is shown in Table 16.8, Which is readable and writable. The value in the mark ium indicates whether the corresponding interrupt is blocked. If ium is 0x0, all interrupts are blocked. If IMU is 0 xffffffff, all interrupts are not blocked. In or1200, the number of bits of ium can be configured. The configuration range is 2-31, because the minimum two bits of ium are always 1, that is, the interrupt source 0 and 1 are set to unblocked, the two interrupt sources can be mapped to power off and system reset.

The format of the interrupt Status Register picsr is shown in Table 16.9, Which is readable and writable. The value in the sign "is" indicates whether the corresponding interrupt occurs and is waiting for processing. "is 0x0" indicates that no interruption occurs. "I" indicates that the I interrupt source has an interruption. The methods used to determine whether an interruption occurs include Level Trigger and edge trigger. or1200 supports Level Trigger. At this time, the I-bit of is actually corresponds to the current level value of the I-th interrupt source.

The or1200 interrupt handling process is as follows:

(1) The interrupt source declares that the interrupt occurred. picsr [I] is 1. If picmr [I] is 1, the processor is notified that the interrupt has arrived.

(2) processor transfer to interrupt processing routine for Interrupt Processing

(3) The interrupt has been processed, and the Interrupt Processing Routine notifies the interrupt source

(4) cancel the interrupt source statement

(5) set the picsr [I] to 0 for the interrupt processing routine and exit the interrupt processing routine.

Note that setting picsr [I] separately does not clear the interrupt. The interrupt source must be notified, and the latter cancels the interrupt declaration.

16.3.2 external connection relationships and macro definitions of PIC

The external connection relationship of the programmable interrupt controller PIC in the or1200 processor is shown in Figure 16.3. The arrows indicate whether the signal is input or output. Interfaces starting with spr_xxx are all signals related to reading and writing of special registers, and their meanings are also clear. In addition, pic_int is an interface with configurable width. The maximum value is 32, corresponds to 32 external interrupt source inputs. When an interruption occurs, the intr interface is used to notify the CPU module. The value 1 indicates that the interruption occurred. The interface sig_int connected to the CPU module also notifies the power management module PM through the pic_wakeup interface, if the processor is in sleep or Doze mode when the interrupt occurs, the PM module returns to normal mode after it receives pic_wakeup as 1. For details, refer to the analysis of the PM module in Section 16.1.

The macros related to the Programmable Interrupt Controller PIC in or1200 are defined as follows:

Or1200_defines.v 'define or1200_pic_implemented // whether to implement the PIC module. The PIC module is an optional module 'fine or1200_pic_ints 20 // defines the number of external interrupt sources, up to 32, the default value is 20 'fine or1200_pic_ofs_picmr 2 'D0 // picmr, and the index of the picsr register in the 9th special registers 'fine or1200_pic_ofs_picsr 2 'd2' define limit 1:0 'fine or1200_pic_picmr // need to define this macro, you can use the picmr register 'define or1200_pic_picsr // you need to define this macro before you can use the picsr register 'define or1200_pic_readregs // with this macro definition, before reading the special registers picmr and picsr in the PIC 'define or1200_pic_unused_zero

 

16.3.3 PIC code analysis

The main code of PIC is to configure the picmr and picsr registers, and determine whether the interrupt occurred based on the values of picmr and picsr. The analysis is as follows (for ease of understanding, I changed the code sequence ):

Or1200_pic.vmodule or1200_pic (CLK, RST, spr_cs, spr_write, spr_addr, spr_dat_ I, spr_dat_o, pic_wakeup, Intr, pic_int );...... Outputpic_wakeup; // output to PM module outputintr; // output to CPU module input ['or1200 _ PIC_INTS-1: 0] pic_int; // input interrupt signal, its width can be configured by or1200_pic_ints 'ifdef effect' ifdef ordef _pic_picmr Reg ['or1200 _ PIC_INTS-1: 2] picmr; // The width of the picmr register is also matched with or1200_pic_ints, but two fewer, // This is because the interrupt source 0, 1 is unshielded, so the width of the picmr is less than the width of the interrupt input // pic_int two 'elsewire ['or1200 _ PIC_INTS-1: 2] picmr; 'endif 'ifdef or1__pic_picsrreg ['or1200 _ PIC_INTS-1: 0] picsr; // picsr Storage The width of the tool also matches or1200_pic_ints 'elsewire ['or1200 _ PIC_INTS-1: 0] picsr; 'endif ...... // If spr_cs is 1, then the minimum two digits of spr_addr determine the instruction L. mfspr/L. the mtspr access target is picmr or picsr // picmr_sel is 1, indicating that the access target is picmr and picsr_sel is 1, indicates that the access target is picsrassign picmr_sel = (spr_cs & (spr_addr ['or1200 _ picofs_bits] = 'or1200 _ pic_ofs_picmr ))? 1 'b1: 1' B0; assign picsr_sel = (spr_cs & (spr_addr ['or1200 _ picofs_bits] = 'or1200 _ pic_ofs_picsr ))? 1 'b1: 1' B0; // combine pic_int with {picmr, 2' B11} to obtain unshielded interrupt information stored in um_ints, note that the source 0 and 1 of the interrupt cannot be blocked. // It has nothing to do with the picmr value. Here it is 2 'b11assign um_ints = pic_int & {picmr, 2 'b11 }; // um_ints is not 0, indicating that an interruption occurs. Set intr to 1 and the sig_int interface assign intr = | um_ints; // after the interruption occurs, you must use the pic_wakeup interface to notify the PM module assign pic_wakeup = intr; 'ifdef or1__pic_picmralways @ (posedge CLK or 'or1200 _ rst_event RST) if (RST = 'or1200 _ rst_value) picmr <= {1 'b1, {'or1200 _ PIC_INTS-3 {1 'b0 }}; else if (picmr_sel & spr_write) begin picmr <= spr_dat_ I ['or1200 _ PIC_INTS-1: 2]; // write picmr. Note that the minimum two values are not affected. End 'elseassign picmr = ('or1200 _ pic_ints) 'b1; 'endif // assign a value to the picsr register. The value of picsr depends on instruction L. the data written by mtspr and the current external interruption. // you can also find that when the interruption occurs, use L separately. mtspr clearing the picsr register does not change the picsr value //, because the value of um_ints is not changed because the interrupt declaration is not canceled by the external device, therefore, the external device must cancel the interrupt statement 'ifdef or0000_pic_picsralways @ (posedge CLK or 'or1200 _ rst_event RST) if (RST = 'or1200 _ rst_value) picsr <= {'or1200 _ pic_ints {1 'b0 }}; else if (picsr_sel & spr_write) Begin picsr <= spr_dat_ I ['or1200 _ PIC_INTS-1: 0] | um_ints; end else picsr <= picsr | um_ints; 'elseassign picsr = pic_int; 'endifalways @ (spr_addr or picmr or picsr) Case (spr_addr ['or1200 _ picofs_bits]) // Synopsys parallel_case 'or1200 _ pic_ofs_picmr: Begin spr_dat_o ['or1200 _ PIC_INTS-1: 0] = {picmr, 2 'b11}; // read picmr, the minimum two digits are always 1 spr_dat_o [31: 'or1200 _ pic_ints] = {32-'or1200 _ pic_ints {1 'b0 }}; end default: Begin spr_dat_o ['or1200 _ PIC_INTS-1: 0] = picsr; // read picsr spr_dat_o [31: 'or1200 _ pic_ints] = {32-'or1200 _ pic_ints {1 'b0 }}; endendcase 'else // If the PIC module is not configured, assign intr = pic_int [1] | pic_int [0]; // If the PIC module is not configured, interrupt 0, 1 can also use assign pic_wakeup = intr; assign spr_dat_o ['or1200 _ PIC_INTS-1: 0] = 'or1200 _ pic_ints 'B0; assign spr_dat_o [31: 'or1200 _ pic_ints] = 32-'or1200 _ pic_ints 'B0; 'endifendmodule

When the interruption occurs, the PIC module sets intr high. See figure 16.3. intr is connected to the sig_int interface of the CPU module, and the exception module inside the CPU receives the signal and processes it, similar to the timer interrupt, it does not immediately respond to the interrupt, but must meet certain conditions to respond, as shown below:

or1200_exception.vassign int_pending = sig_int & (sr[`OR1200_SR_IEE] | (sr_we & to_sr[`OR1200_SR_IEE]))                     & id_pc_val & delayed_iee[2] & ~ex_freeze & ~ex_branch_taken                       & ~ex_dslot & ~(sr_we & ~to_sr[`OR1200_SR_IEE]);

The description of each condition refers to the timer interruption. When the condition is met, int_pending is 1, and the processor enters the External Interrupt exception handling process. The specific process is the same as the timer interruption.