PLL principle && clock generation method for phase-locked loop

The PLL is an abbreviation for the phase-locked Loop, and the Chinese meaning is a phase-locked loop. The PLL is essentially a closed-loop feedback control system that allows the PLL output to maintain a fixed phase relationship with a reference signal. The PLL is typically composed of a phase detector, a charge amplifier (Charge Pump), a low-pass filter, a voltage-controlled oscillator (electrical), and some form of output converter. To make the PLL's output frequency a multiple of the reference clock, the divider can also be placed on the feedback path or (and) reference signal path of the PLL. The functional schematic of the PLL is shown in the following figure:

The voltage-controlled oscillator produces a periodic output signal, if its output frequency is lower than the reference signal frequency, the phase detector through the charge amplifier to change the control voltage so that the voltage-controlled oscillator output frequency increased. If the output frequency of the voltage-controlled oscillator is higher than the frequency of the reference signal, the phase detector changes the control voltage through the charge amplifier so that the output frequency of the voltage-controlled oscillator is reduced. The function of the lowpass filter is to smooth the output of the charge amplifier, so that the system tends to a steady state when the phase detector is slightly adjusted.
Basic applications for PLLs include:

(1) Clock recovery.

(2) Offset correction: In the transmission process of the signal, the process, temperature, voltage will affect the clock along with the data Sampling window delay, this delay limits the frequency of data transmission. One way to solve this problem is to use the offset correction PLL at the receiving end of the data to eliminate this delay, so that the clock signal for each sample trigger is matched to the receive clock phase.
(3) Clock generation: Most electronic systems today contain different kinds of processors. Typically, the external provides a lower clock frequency for the processor and then uses the PLL in the processor to multiply or divide it to the clock frequency required by the processor.

Another about the concept of charge pump charge pump, add as follows: Charge pump is the use of capacitance of the impulse discharge to achieve voltage conversion, input circuit and output circuit rotation conduction. The output voltage is regulated by adjusting the duty ratio. A charge pump, also known as a switched-capacitor voltage converter, is a DC-V converter that uses so-called "fast" (flying) or "pumped" capacitors (rather than inductors or Transformers) to store energy. They can increase or decrease the input voltage and can also be used to generate negative voltages. Its internal FET switch array controls the charging and discharging of the fast capacitor in a certain way, thereby multiplying or lowering the input voltage by a certain factor (0.5,2 or 3), thus obtaining the desired output voltage.

=============================================================================================================== =====

The three basic conditions for a CPU operation are: voltage, clock, reset signal. Then the external clock to produce a variety of methods: (1) Crystal, it needs to match the oscillation circuit and excitation signal can produce frequency, the oscillation circuit can be external or inside the chip, (2) Crystal oscillator, itself has an external oscillation circuit, (3) external provide clock input.

Reference Original: http://www.eefocus.com/html/dict_123699_81628a33e0a2f1f718f49abf1c23bebd.html