With the development of PowerPC, the use of PowerPC architecture of the processor has formed a huge family, in communications, industrial control, aerospace defense and other requirements of high-performance and high reliability of the field has been widely used, is a "noble chip." At present, there are few Chinese materials to elaborate the PowerPC family pedigree, it is a regrettable thing. This article will give beginners a brief introduction to the PowerPC family.
It is not an easy thing to articulate the development of PowerPC.
"PowerPC"The word, it is easy to confuse, especially IBM registered a series of related trademarks. Like what
Power、
Power PC、
PowerPCThese three words have more than 3 meanings, and it takes an engineer's clever mind to distinguish them. In general, the PowerPC refers to the processor using the PowerPC instruction set.
In the the 1990s, IBM (International Business Machine), Apple and Motorola (Motorola) jointly developed the PowerPC processor.
PowerPC, the original meaning is not power, but performance optimized with enhanced RISC;PC refers to performance Computing.
At present, the mainstream PowerPC processor manufacturers have IBM, Freescale™semiconductor (formerly Motorola Semiconductor Division), AMCC, LSI and so on. One of the most popular PowerPC processors is IBM and Freescale. This article on the two companies based on the PowerPC processor, started to tell the PowerPC family.
IBM's PowerPC family
IBM currently has a total of 3 major PowerPC processing series: Power, Power pc and cell. Power,power PC Center, there is also a Star series.
Power SeriesThe CPUs were manufactured from 1990 and equipped to rs/6000 (i.e. RISC system/6000) UNIX workstations and servers, now known as eserver™pseries® servers (the latest name is the Power System P series), The main models are the Power 1,power 2™,power 3™,power 4™,power 4+, as well as the current power 5,power 5+ and the Power 6 processor just launched.
The first 801 was the predecessor of the Power series processor, its design is very simple, in order to achieve all the instructions can be completed within a clock cycle, so the lack of floating-point operations and parallel processing capabilities, the power architecture to solve this problem, or beyond the 801 limit, increased to more than 100 instructions, Become a very "complex" compact instruction set CPU.
1. Power 1
Released in 1990, each chip encapsulates about 800,000 transistors.
Unlike other processors at the time, Power 1 has a functional partition, which makes it very scalable, with separate floating-point registers that can be applied to a variety of environments from low-end UNIX workstations to high-end UNIX servers. The earliest power 1 was a combination of several chips installed on the same motherboard, but was quickly integrated into a single chip design, with a total of over 1 million RISC processors (Rsc,risc single Chip, the one-chip RISC processor). The most successful application of power 1 was used in the Mars Pathfinder spacecraft.
2. Power 2
Released in 1993, each chip encapsulates 15 million transistors.
Power 2 Adds a second floating-point unit processing (floating-point UNIT,FPU) and more caching. The super chip called P2SC (Power 2 Scalable Chip) uses cmos-6s technology to implement the POWER2 8-kernel architecture from a single chip (from here you can see that in 1993 IBM had already started a multi-core chip design, in fact, if mainframe, In the 1980s, there was the idea of multi-core, the 32-node Deep Blue (navy) supercomputer that used the processor, which defeated the chess champion Kasparov in 1997.
3. Power 3
Released in 1998, each chip encapsulates 15 million transistors.
This is IBM's first 64-bit symmetric multiprocessor architecture (SMP), fully compatible with the original power instruction set, and also compatible with the Power PC instruction set, mainly for scientific computing, from aeronautical design, biopharmaceutical data analysis to weather forecasts. It has a data prefetch engine, a non-blocking built-in data cache, and a dual floating-point processing unit. The power 3-ii uses the same design as Power 3, which uses copper conductor technology to make chips, and improves performance by at almost the same cost of manufacturing.
4. Power 4
Released in 2001, each chip encapsulates 174 million transistors.
This is a processor up to GHz, 0.18 micron copper wire, silicon insulation technology. It has all the features of power 3, including compatibility with the Power PC instruction set, but it is also a new design with two 64-bit 1ghz+ Power PC cores per processor, the industry's first single chip dual-core design for mass production, Also known as a single chip symmetric multiprocessing design (multicore in a a single die,smp on a chip, or system on a chip), each processor can execute 200 instructions at the same time. The Power 4 architecture can be used to build a large IBM regatta (ie p690) server and also to design the Power PC 970 processor (known as Apple G5). Power 4+™ (also known as Power 4-ii) is an improved version of the Power 4 frequency upgrade. The Power 4 CPU supports partitioning technology, which allows chips to be cut into multiple units to run different operating systems.
5. Power 5™
Released in 2004, similar to power 3 and Power 4, the Power 5 also uses the power and Power PC architecture, leveraging faster in-chip communication technology, chip-processing technology, and simultaneous multithreading (simultaneous multithreading), SMT, a physical CPU core can simulate two logical CPUs, if the two threads of the work content of a large difference, the use of SMT technology performance can achieve a single CPU to perform the 1.5~1.7 times, than the Power 4 performance increased by 4 times times. Power 5 's high-end server code-named "Cavalry" ("Squadrons"), IBM wanted the CPU to be like the Knight Colts charge as sweeping the UNIX server market, the result seems to fulfill the designer's expectations. The function of the differential zone (Advanced virtualization) is supported on Power 5, and a processor kernel can be virtual cut into multiple processors for the operating system, with a minimum allocation granularity of 0.1 CPUs and a shared granularity of 1/100 CPUs. In 2006, IBM unveiled the Power 5, the Power 5+, which is the highest frequency of 2.2GHz.
6. Power 6™
Released in May 2007, the current maximum frequency of 4.7GHz, the highest next year will have more than 5GHz frequency version. In-chip integration is about 750 million transistors. Power 6 integrates some bus controls with the data channel between the CPU cores into a single chip, adding more communication mechanisms and cache to the CPU cores than Power 5. Power 6 has the characteristic technology that can directly support the 10 digital processing, this is a regression in the history of computers, we go from decimal to binary to facilitate computer processing, and today, the computer chip design is sufficiently advanced, so that we can no longer adapt to the machine, but let the machine adapt to our needs.
Power 6 other technologies include dual cores, 128KB L1 cache (data, instructions 64KB), 8 two-order pipeline support in a clock cycle to complete two sets of 32-bit read or a 64-bit write operation, two cores each have 4MB "half share" L2 Cache, although it is occupied by a kernel, But another kernel can quickly access it; another 32MB L3 cache can be accessed by two cores via 80gb/s bandwidth, and power 6 also improves vector processing performance through ViVA-2 (Virtualvector architecture) technology ; supporting up to 1024 virtual partitions is also a new feature of Power 6 (the Power 5 supports up to 256 partitions). The Power 6-specific 10-binary operation registers, instructions can make it in the calculation does not produce 2-10 conversion error, but also improve the operation speed. Power 6 includes some extra circuitry to support mainframe's instructions, starting the practice of integrating the Z-series, while Power 6L is a "simplified" version of the chip, which lowers the frequency and can be used for the blade server.
At the same time that power 6 was produced, Power 7 was in a tight development phase and is expected to be available in 2012.
Star Series Processorsis another technology implementation of the Power PC architecture, very similar to the power series. Because the various CPU codes for this series are named after star or with the name of a certain star, they are called the Star series.
1. RS64
1997 issued, code-named "Apache".
This series is designed using the Power PC processor, inherited a large number of power architectures, but specifically optimized for commercial operations, compared to the Power 3, including instruction branch prediction, floating-point unexpected processing, hardware prefetching, and other functions were canceled, and replaced by the plastic calculation of unexpected processing, complex in-chip /Slice out cache algorithm, larger cache capacity. RS64 's design can support 64-bit processing, in 2000 released RS64 IV, the use of hardware multithreading technology, a single server can be expanded to 24 CPUs, consumes a very small amount of power, each processor only 15 watts. This CPU is used for as/400 (i.e. later iseries) and is used for rs/6000 (pseries) from RS-II.
This design makes RS64 chips more suitable for online transactions (on-line Transaction PROCESSING,OLTP), Enterprise Resource planning systems (Enterprise Resource), and other large, Mixed multi-function, database access, multi-user, multi-process business. However, in the actual use of the process, found that its computational speed is slightly deficient, may be RS64 CPU is very low frequency, typical of several server frequency only about 100MHZ, for business intelligence (Business INTELLIGENCE,BI) and scientific calculation of a class of applications, poor performance.
2. RS64 II
1998 issued, code-named: "Northstar" (North Star).
The CPU has 8MB L2 cache,256 bit data bus, 262MHz frequency. The server that assembles this CPU can support up to three CPU boards, and each CPU board is loaded with 4-way CPUs, which enables the rs/6000 server to have 4, 8, 12-way SMP structures.
3. RS64 III
Issued in 1999, code-named: "Pulsar" (pulsar).
The first silicon-insulated RS64 chip can achieve 24-way SMP structure with 6 CPU cards. As the CPU frequency increased to 450MHz, the use of optimized instruction branch prefetching technology to avoid the jump penalty (or only need an additional 1 clock cycle), 5-level pipeline technology, CPU processing performance greatly improved. IBM uses this server to assemble the rs/6000 80 series (H80,M80,S80 server).
4. RS64 IV
2001 issued, code-named: Istar,sstar
The first commercial processor that supports hardware multithreading is faster and smaller than the same series of CPUs in the past. 600-750mhz's frequency, hardware multithreading technology (HMT) makes this CPU has a good market performance. In addition, each CPU consumes only 15W of power and the server that is assembled with this CPU does not need a special power supply or cooling system.
Because of the mixed demand for business and computing environments, IBM has consolidated the power series and Power PC series processors, eventually designing the Power 4 processor. The Star series also completed its historical mission.
Power PC Series, a branch of power architecture that was first released in 1993 for use from single board, battery-powered management to supercomputers and mainframe hosts. The Power PC first landed on the lead as a CPU from power Macintosh 6100.
As we all know, the Power PC started with the Apple, Motorola and IBM alliances (known as Aim Federation), originated from the Power architecture design, but made a lot of changes. For example, the Power PC is a Open-endian design that supports both the large end segment (Big-endian) and the small Tail segment (Little-endian) memory mode, while power is the large end segment design; Power PC wants to provide stronger floating-point processing and multithreading capabilities. So there is not much difference between the two types of CPUs, the Power PC retains most of the power commands, and many applications can be run on two separate platforms as long as they are recompiled.
When IBM and Motorola design their own chips, they still follow a uniform standard. In 2000, the book E spec was used, which enabled the Power PC to focus more on embedded processing systems, such as networks, storage, and home-utility processors.
In addition to being compatible, another bright spot of the Power PC's architecture is openness, which exposes instruction sets that allow any vendor to design a compatible processor for a Power PC, and the source code for some of the Power PC's software can also be downloaded, and the Power PC's kernel is very small, Many other auxiliary circuits, such as caching and coprocessor, can be placed on the same chip, which greatly increases the flexibility of the chip.
Two of the IBM four server product lines are related to the Power PC architecture, and Apple's desktop and server, Nintendo's GAMECUBE,IBM, and its own blue Gene supercomputer use PowerPC chips.
Today, the Power PC family has three product lines, namely the embedded Power PC 400 series, the Power PC 700 and the Power PC 900 series. Historically, there is also a power PC 600 series that is most noteworthy because of its excellent performance.
1. Power PC 600 Series
Power PC 601, the first in the Power PC 600 series, combines the features of the power and Power PC architectures and maintains compatibility with power 1 and other Power PC chips that follow, even in the same series of chips. Even with Motorola's 88110 compatibility. Apple built the Power MAC 6100,66 MHz CPU frequency in 1994 with power PC 601. The next chip in this series is 603, a low-end, low-power processor that is used heavily on automobiles. The PowerPC 604®, which comes on the same day as power PC 603®, is a more powerful processor, followed by 603e and 604e of "Enhanced Edition". After that, the first 64-bit power Pc--power PC 620® was released in 1995.
2. Power PC 700 Series
In 1998, the Power PC 740 and Power PC 750 appeared, very much like 604e, and some people said that the 600/7,002 series was the same thing. Power PC 750 is the first copper conductor processor that Apple used to produce G3, but was soon replaced by G4, using Motorola 7400. The 32-bit power PC 750FX, released in 2002, had been a shock to the industry because it was the first processor to reach 1GHz, with IBM in 2003 followed by 750GX, integrated 1MB Two-level cache, and 1GHz's frequency, about 7 watts.
3. Power PC 900 Series
The 64-bit power PC 970, which is actually a single processor kernel, is 4 and can execute 200 instructions at the same time, up to a maximum of 2 GHz, and consumes only a dozen watts of electricity. Low power makes it widely available for laptops and handheld devices, as well as high density storage, servers (such as blade centers). 64-bit processing capability, single instruction multiple data flow design makes it more suitable for multimedia, graphics processing. Apple's desktops, Xserve servers, and other graphics and networking devices are using this processor. Apple Xserve G5, for example, uses the power PC 970FX and is the first chip to use both the strain silicon and silicon insulation technology.
4. Power PC 400 Series
This chip is mainly used in embedded systems, but the Power PC's flexible architecture allows it to be used from small devices such as set-top boxes to blue-gene supercomputers. At one end of the product line, the Power PC 405EP consumes only 1 watts of electricity at 200MHz, while the copper-conductor 440 at MHz can provide the highest performance in the same type of embedded chips. This chip also has a number of offshoot, such as using the power PC 440GX dual Gigabit Ethernet and TCP/IP acceleration to reduce network applications over 50% of the load. Around the Power PC 400 kernel, there are many concrete implementations that the processing chip used to build the Blue Gene supercomputer is comprised of two power PC 440 processor cores and two floating-point processing cores.
The Power PC 400 series was transferred to AMCC by IBM and developed into a 3 series of PowerPC 405 Family, PowerPC 440 Family, PowerPC 460 and Family.
Freescale PowerPC Series
The Freescale Company offers a large number of PowerPC processors with integrated, and has achieved considerable success in the network equipment market. At present, Freescale Company has adjusted its PowerPC product strategy, dividing it into 3 major markets: Network equipment, automotive Electronics (MPC5XX series) and industrial control.
Freescale PowerPC's success in communications is likely to be attributed to power QUICC, which is also the most important difference between IBM's PowerPC and Freescale's PowerPC. In 1993, Motorola Semiconductor Division (formerly known as Freescale Semiconductor) produced the first chip Controller containing QUICC (Quad integrated Communications--mc68360) on the basis of fully understanding the application of the communication system. At this point, QUICC is actually a separate processor. In 1994, Motorola Semiconductor engineers began to combine the QUICC and PowerPC cores of MC68360 to call the PowerPC processor, which integrates QUICC, as the power QUICC, and called the QUICC Processing module CPM.
1995, the MPC860 chip market, marking the beginning of a communication processor era. The chip realizes the separation of the PowerPC processor as the control center and the CPM as a data processing center, using the idea of separating the data path and the control path.
Since then power QUICC series chips have also been upgraded, from power QUICC I to power QUICC II, to power QUICC III and Power QUICC II Pro. Currently, Freescale is upgrading CPM to QE (QUICC Engine).
Along with the power QUICC upgrades, the Freescale PowerPC kernel is also being upgraded.
Of
603 Core Series: MPC850, MPC860, MPC875, MPC885, etc., is currently the lowest end of the Freescale PowerPC processor. This type of PowerPC processor does not contain an SDRAM interface, and the user must configure the SDRAM interface with the UPM (user programmable machines) provided by MPC860. 603 kernel with power QUICC I.
603E Core Series: MPC8250, MPC8260, MPC8272 and so on. From the PowerPC kernel point of view, 603 to 603E upgrade is not large, mainly MMU, in addition to include SDRAM controller. 603E kernel with power QUICC II.
E300 Core Series: MPC8349, MPC8347, MPC8360 and so on. The E300 series is basically consistent with the 603E series structure, with little modification on the processor kernel. QE is first implemented on the MPC8360 and also supports the DDR SDRAM interface. E300 kernel with power QUICC II Pro.
E500 Core Series: Including MPC8540, MPC8560, MPC8548 and so on. The E500 kernel has a total of V1, V2 two versions. The biggest difference between the V1 version and the V2 version is MMU. The PowerPC processor based on E500 kernel is the development direction of Freescale high-end processor. The E500 kernel differs greatly from the 603E, except that the instruction system is compatible and the other kernel components are not the same. The E500 kernel supports DDR Sdram,rapidio and Gigabit Ethernet interfaces. E500 core with power QUICC III.
E600 Core Series: Also known as G4, including mpc7410,mpc7447,mpc7448,mpc8641 and so on. The biggest difference with the IBM Power 700 series is that the G4 series supports AltiVec architecture. Such processors are also apple chips for Mac machines.
E700 Series: Support for 64-bit PowerPC structure, in development (the latest news is unknown, suspected to be abandoned).
Freescale QorIQ Communication platform is the next generation evolution product of Freescale's POWERQUICC communication processor, containing one or more cores, a total of 5 different product platforms. According to function and performance, it is divided into P1, P2, P3, P4 and P5, keeping software compatible with old PowerPC products, such as POWERQUICC platform.
The QorIQ trademark and P1, P2, P4 product family were released in June 2008, and details of the P3 and P5 platforms have not yet been made public. All QorIQ processors are based on the E500 or e5500 core. The P10XX and P20XX series are based on the E500V2 core, the P340XX and P40XX series are based on the E500MC core, and P50XX is based on the e5500 core.
P1 Series
The P1 series is designed for gateways, Ethernet switches, wireless LAN access points, and universal control purposes. The P1 series is entry-level and runs at 400 to 800MHz, replacing POWERQUICC II Pro and POWERQUICC III platforms. The P1 series is packaged into 689 pins, compatible with the P2 series.
P1011-Contains a 800mhze500 core, 256 KB L2 cache,4 serdes A Gigabit Ethernet controller, and a time division multiplexing engine for Honest telephony (TDM lanes,3).
p1020– contains 2 MHz E500 cores, 256 KB shared L2 cache, 4 SerDes lanes,3 Gigabit Ethernet controllers, and one TDM engine.
P2 Series
P2 Series design for the network, telecommunications, military and wide application. Can run in-40 to 125°c, especially for applications under harsh conditions. The P2 series belongs to midrange products and runs at 800Mhz to 1.2GHz, replacing POWERQUICC II Pro and POWERQUICC III platforms.
p2010– contains 1 1.2 GHz cores
p2020– contains 2 1.2 GHz cores, shared L2 cache
P3 Series
The P3 series design is a midrange product for switches and routers. The P3 series provides a multi-core platform that supports 4 E500MC cores, each with a core frequency of 1.5 GHz. The P3 series has a 1.3 GHz 64-bit DDR3 memory controller, 18 SerDes lanes, and hardware accelerators for packet operations and scheduling, regular expressions, RAID, security, encryption, and RapidIO.
Multiple cores of the P3 series can run in symmetric and asymmetric modes, meaning that multiple cores can run the operating system together or not.
P3041-4 a 1.5 GHz core, each core 128 KB L2 cache, 1 1.3 GHz 64-bit DDR3 memory controller, 45 nm technology and only 12w of power.
P4 Series
The P4 series belongs to high-end products for core networks or enterprise switches and routers. Provides a limit multi-core platform that supports 8 E500MC cores, each of which reaches 1.5 GHz.
The p4080– contains 8 E500MC cores, each with 32/32kb Instruction/data L1 caches and 1 a 128 KB L2 cache. Contains 2 1 MB L3 caches, each connected to the 64-bit DDR2/DDR3 memory controller.
P5 Series
The P5 series is based on the high-performance 64-bit e5500 core and is increased to 2.5 GHz. June 2010 Introduction, may be at the end of 2010 can be samples, 2011 can be mass-produced.
P5010-A e5500 2.2 GHz core, 1 MB L3 cache, 1 DDR3 controller,45 nm process, power 30W.
P5020-Two e5500 2.2 GHz Core, 2 1 MB L3 caches, 2 DDR3 controllers, NM process, power 30W.
