Quartus II + Modelsim simulation

ArticleDirectory

• 1. design verification process of FPGA
• 2. Concepts and steps of simulation steps
• Iii. Perform Function and timing simulation on Quartus II
• Iv. Q2 + Modelsim for Function & timing simulation

Quartus II + Modelsim simulation

Crazybingo

2012-3-2

For more information, see the blog post of the previous generation of wushuang OO:

Http://www.cnblogs.com/oomusou/archive/2009/01/30/modelsim_pre_post_simulate.html

Reference Book: the second edition of Altera FPGA/CPLD design

1. design verification process of FPGA

Figure 1: complete FPGA/CPLD design process

Figure 2: Brief FPGA/CPLD design process

Figure 3: compiling steps in Quartus II

2. Concepts and steps of simulation steps

1) pre-Simulation

The front simulation, that is, functional simulation, uses a dedicated tool to simulate the design, verify whether the circuit function meets the design requirements. Functional simulation can speed up the design progress and improve the design reliability even if design errors are found.

2) Integrated Simulation

Marking the standard delay generated by synthesis to the integrated simulation model can estimate the impact of the door delay, but only the door delay can be estimated, and the line delay cannot be estimated, there is still a certain gap between the simulation results and the actual situation of the Department, which is not very accurate.

Because the current integrated tools are relatively mature, simulation of this link is generally omitted. In Quartus II, perform the next simulation directly.

3) Layout and wiring Simulation

Instant sequential simulation. The most comprehensive simulation latency file generated after layout and wiring includes not only the door latency, but also the wiring latency. Therefore, it is the most accurate and can better reflect the actual work of the chip.

In general, layout and wiring must be carried out to ensure the reliability and stability of the design and to detect timing violations (timing violation ).

4) Board Simulation

In some cases of high-speed design, we also need to use a third-party board-level verification tool for simulation and testing, enter mentortau, Forte design-timing designer, mentor hyperlynx, mentor icx, Cadence specctraquest, and Synopsys HSPICE. These tools can analyze the circuit characteristics such as signal integrity and electromagnetic interference (EMI) of high-speed design through the simulation of ibis and HSPICE models.

5) online simulation

After loading the configuration target board, the designer needs to perform a step, that is, online simulation and debugging, using the us II built-in SignalTap II online logic analyzer for analysis, through the JTAG port, reads FPGA internal signals online and in real time.

In our design, but in our small design, timing simulation can be omitted if the timing requirements are not very strict, only functional simulation is performed (the Integrated Simulation is generally used only in the IC design. The general software is competent for comprehensive work, and the entire compilation process is integrated directly → layout and wiring ); when a large design or timing sequence is very rigorous, timing simulation must be performed to verify whether the timing sequence is in violation and then use timequest for constraints (static timing analysis (STA) embedded in Quartus II can be used ), or a third party (fprmality and primetime of Synopsys), you can also use the chip editor embedded in Quartus II to analyze the internal connection of the chip for configuration .). In addition, in high-speed circuit design, in order to ensure the reliability of the design, it is necessary to carry out some board-level verification after timing simulation.

Iii. Quartus II Functions & timing simulation (1) Quartus II Simulation

Even if no third-party software is needed, Quartus II can also perform functional simulation and timing simulation on its own. However, the Waveform Simulator is not suitable for large time series, and the GUI just makes a comparison stamp.

In the us II simulation, the software is divided into "function" and "Timing", as well as a fast time series simulation model, that is, functional simulation and time series simulation, which can be set in the simulator setting clock of the device. Generally, timing simulation is performed directly or by default.

(2) functional simulation

(1) set simulator to functional function simulation in setting

(2) generate a functional simulation network label File

(3) perform functional simulation after the incentive is input, as shown in:

(3) timing simulation

(1) Select timing simulation in simulation setting

(2) Start simulation. For example, you can see the time series latency (door-level latency and wiring latency)

Iv. Functions of Q2 + Modelsim & timing simulation (1) Modelsim simulation

ModelSim is the best language simulator in the industry, but it is more professional and awesome. For large projects and complex time series, If You Want To input incentives like Quartus II, wait and wait ......

Compared with Quartus II, Modelsim also provides function simulation and time series simulation, but function simulation can be self-sufficient, and time series simulation can only be performed using the network standard file. VO after the integration of Quartus II.

For the convenience of users, Altera directly released The Modelsim Of The Altera version. Of course, the corresponding version must be used for automatic simulation.

When the software version requirements are met, you must set a third-party software path in Quartus II tool → option, as described below:

For Xiao Bai (I am Xiao Bai), Modelsim can automatically run on the Quartus II settings for timing simulation or functional simulation. However, Altera software is called RTL-level simulation and gate-level simulation, which correspond to functional simulation and timing simulation respectively.

(2) functional simulation

(1) set it in Quartus EDA tool setting → simulate

For example, during function simulation, you do not need to choose to perform gate-level (timing simulation) after compilation)

(2) set the automatically generated function to simulate the network logo

(3) Add the testbench File

(4) Compile and run RTL simulation, that is, functional simulation

(5) Quartus II + Altera Modelsim will automatically complete various Modelsim settings until the simulation ends, as shown below:

(3) timing simulation

(1) In the initial setting, if the system automatically performs the gate-level simulation (timing simulation) after compilation is selected, the software will automatically perform the simulation after compilation and the simulation is completed. The settings are as follows:

(2) Of course, you can also directly run gate level to simulate real-time sequential simulation based on functional simulation.

(3) Quartus II + Modelsim is automatically loaded. The timing simulation results are shown in:

(4) lazy debugging

After functional simulation or the last step of time series simulation, the simulation result of Modelsim has been displayed. At this time, you can perform "depth" debugging:

(1) Run 500ns to increase simulation time

(2) reset restart and try again

(3) modify the testbench test file, recompile the testbench file, and continue debugging.

(4) It is recommended that you create a project in Modelsim to run the project independently. Predict the results and listen to the next decomposition!