RCC for stm32

Meanings of stm32 clock system:

1. Power Switch to achieve low power consumption;

2. Adjust the clock speed;

For each peripheral, you must set the clock system of stm32 to reduce power consumption;

Analysis of stm32 clock system block diagram: clock source:

The clock is the pulse of stm32 and the driver source. When using any peripherals, the corresponding clock must be turned on. The advantage is that if you do not use a peripheral, you can turn off its clock to reduce the power consumption of the system, save energy, and achieve low power consumption;

The stm32 clock can be provided by the following four clock sources:

1. HSI: high-speed internal clock signal stm32 MCU internal clock (8 M frequency), disadvantage is poor accuracy;

2. HSE: high-speed external clock signal, high precision Source: (1), external crystal oscillator (2), HSE user external clock;

3. LSE: Low-speed external crystal oscillator 32.768khz mainly provides a precise clock source, which is generally used as an RTC clock;

4. LSI: provides an internal low-speed clock with an independent watchdog or RTC;

Stm32 divides the clock signal (such as HSE) by frequency division or frequency doubling (PLL) to obtain the system clock. The system clock is divided by frequency to generate the clock used by the peripherals;

RCC setting process:

1. Reset the RCC register to the default rcc_deinit value.

2. Enable the external high-speed clock crystal oscillator HSE rcc_hseconfig (rcc_hse_on)

3. Wait for the external high-speed clock crystal oscillator to work hsestartupstatus = rcc_waitforhsestartup ();

4. Set the AHB clock rcc_hclkconfig

5. Set the high-speed APB clock rcc_pclk2config

6. Set the low-speed APB clock rcc_pclk1config

7. Set PLL rcc_pllconfig

8. Enable PLL rcc_pllcmd (enable)

9. Wait for the PLL to work while (rcc_getflagstatus (rcc_flag_pllrdy) = reset)

10. Set the system clock rcc_sysclockconfig

11. Determine if the PLL is a system clock while (rcc_getsysclksource ()! = 0x08)

12. Enable the peripheral clock rcc_apb2perphclockcmd ()/rcc_apb1periphclockcmd ()

Instance:

1 /************************************** **************************************** * 2 * Function Name: rcc_configuration 3 * Description: configures the different system clocks. 4 * input: None 5 * output: None 6 * return: none 7 ************************************** **************************************** */8 void rcc_configuration (void) 9 {10/* ------ use an external RC crystal oscillator ---------- */11 rcc_deinit (); // clock 12 rcc_hseconfig (rcc_hse_on) is initialized by default; // enable the external high-speed clock 13 while (rcc_getflagstatus (rcc_flag_hserdy) = reset ); // wait for the external high-speed clock to Be Ready 14 15 flash_prefetchbuffercmd (bytes); // enable command to pre-access 16 flash_setlatency (flash_latency_2); // wait for two cycles 17 18 rcc_hclkconfig (rcc_syscl ); // set the AHB clock to the system clock 19 rcc_pclk2config (rcc_hclk_div1); // set the apb2 clock to the AHB clock 20 rcc_pclk1config (rcc_hclk_div2 ); // set apb1 clock to AHB/2 clock 21 // The following three rows are the PLL settings 22 rcc_pllconfig (Listen, rcc_pllmul_9); // set the PLL clock to the 9-harmonic 23 rcc_pllcmd (enable) of the external high-speed clock; // enable the PLL clock 24 while (rcc_getflagstatus (wait) = reset); // wait for the PLL clock to be ready. 25 // select clock26 rcc_sysclkconfig (rcc_sysclksource_pllclk) for the PLL ); // configure the PLL clock to the system clock 27 while (rcc_getsysclksource ()! = 0x08); // wait for the PLL clock as the system clock 28 29 rcc_apb2periphclockcmd (rcc_apb2periph_gpioc); 30 rcc_apb1periphclockcmd (enabled, enable); 31}

RTC module:

RTC (real_time clock) Real-time clock;

The real-time clock is an independent timer. The RTC module has a set of counter with consecutive counts. With the corresponding software configuration, the clock Calendar function can be provided. You can modify the counter value to reset the current time and date of the system;

RTC consists of two main parts. The first part (apb1 Interface) is used to connect to the apb1 bus. This unit contains a set of 16-bit registers that can be read and written through the apb1 bus. The apb1 interface uses the apb1 bus clock as the clock;

The other part (RTC core) consists of a series of programmable counters and is divided into two main modules;

The first module is the pre-division module of RTC, which can generate a RTC time reference tr_clk with a maximum of 1 second, the RTC pre-divider module contains a 20-bit programmable divider (RTC pre-divider ). In each tr_clk cycle, if the corresponding allowed bits are set in the rtc_cr register, RTC will generate an interruption (in seconds)

The second module is a 32-bit programmable counter, which can be initialized to the current system clock time. The system time increases at the tr_clk speed and is compared with the programmable time stored in the rtc_alr register. If the rtc_cr control register is set to allow, an alarm is interrupted when the comparison matches;

RTC main features:
?? Programmable pre-division coefficient: the highest frequency division coefficient is 220.
?? A 32-bit programmable counter that can be used for measurement over a long period of time.
?? Two separate clocks: The pclk1 and RTC clock used for the apb1 interface (at this time, the RTC clock must be smaller
More than 1/4 of pclk1 clock)
?? Two independent reset types:
-Apb1 interface reset by System
-RTC can only be reset by the backup domain.
?? Three specialized shielded interruptions:
-An alarm interrupt is used to generate a software-programmable alarm interrupt.
-Second interrupt, used to generate a programmable periodic interrupt signal (up to 1 second ).
-Overflow interrupt: detects internal programmable counter overflow and returns to 0.

　　

Some RTC settings are saved in the backup area: rtc_prolactin, rtc_alr, rtc_cnt, and rtc_div registers;

These registers can only be reset through the backup reset signal, not affected by the system reset or power reset;

Backup region Reset:

When one of the following times occurs, the backup region is reset:

1. Software reset and backup region reset can be performed by setting bdrst bits in the backup region controller rcc_bdcr;

2. If the backup battery and system power supply are not powered, reset the backup area;

Configure RTC:

There are two RTC modes (work mode and configuration mode). to configure RTC, first set RTC to be in the configuration mode; enable RTC to enter the configuration mode through the CNF position in the rtc_crl register. In addition, write operations on any register of RTC must be performed after the previous write operation is completed, to use the software to query the current status, you can query the rt0ff status bit in the rtc_cr register to determine whether the RTC register is being updated. Only when the rtoff status bit is "1, new values can be written to the RTC register. (These are protection measures for RTC)

Configuration process:

1. query the rtoff bit until the rtoff value changes to "1"

2. Set the CNF value to 1 to enter the configuration mode;

3. Write one or more RTC registers;

4. Identify the CNF flag and exit the configuration mode;

5. query rtoff until the rtoff bit changes to "1" to confirm that the write operation has been completed;

Write operations can be performed only when the CNF flag is cleared. This process requires at least three rtcclk cycles;

// To be continued ....

　　

 

RCC for stm32