SDRAM Learning Notes (i)

First, the SDRAM initialization process:
1, send _PR (precharge) command.
2, meet the TRP time requirements of at least 20ns.
3. Send _ar (Auto Refresh) command.
4, Meet TRFC (Trpc aka TRCC) time requirements of at least 63ns.
5. Send _ar (Auto Refresh) command.
6, Meet TRFC (Trpc aka TRCC) time requirements of at least 63ns.
7, send _LMR (lode moderegister) command and related configuration information.
8, meet the TMRD time requirements of at least 1 clocks.

Two, SDRAM operation command:

1, precharge--release all the resource pool, TRP is the time required to release;
2, Auto refresh--internal data refresh automatically, that is, the recovery of capacitance. TRFC (aka TRCC) is the time requirement for automatic refresh;
3. SDRAM has two-layer timing requirements:
The first layer is TRP, TRPC, TMRD, the second layer is TCMS, TCMH, TAS, Tah and so on;
The first layer is called the basic time requirement of the SDRAM operation, and the second layer is called the time requirement for the hardware's own behavior (or the delay time of the path).

4. SDRAM sets (updates) data on the falling edge of the clock signal; the rising edge of the clock signal (read) latches the data.

5, SDRAM need at least 100US of hot time (SDRAM power after the initialization time required).

6, T1 when the driver (FPGA) Send command Precharge, where A10 and ba0~1 accompanying related data.
(1), all A10 for 1,dram are released, at this point the selection of ba0~1 is not valid.
(2), A10 0, SDRAM will be based on the choice of ba0~1 to release the relevant resource pool. At this point, the driver (SDRAM) does not have a related operation.

7.

SDRAM Learning Notes (i)