Verilog Array for Synthsis

Integer i,j;
Always @ (Posedge i_clk or Negedge i_rst_n) begin
if (!i_rst_n) begin
for (i = 0; i < i_wghtgridh; i = i + 1) begin
for (j = 0; J < i_wghtgridw; j = j + 1) begin
R_WEIGHTONWEIGHTS0A[I][J] <= 5 ' d0;
End
End
End
ELSE begin
R_WEIGHTONWEIGHTS0A[TEXEL_CNT_Y_R2][TEXEL_CNT_X_R2] <= W_weightonweights0;
End
End
Why design compiler-think this isn't right?
Because I_wghtgridh is a variable.

This is OK.
reg [4:0] r_weightonweights0a [7:0][7:0];
Integer i,j;
Always @ (Posedge i_clk or Negedge i_rst_n) begin
if (!i_rst_n) begin
for (i = 0; i < 8; i = i + 1) begin//NUM_PLP can use wire??
for (j = 0; J < 8; j = j + 1) begin
R_WEIGHTONWEIGHTS0A[I][J] <= 5 ' d0;
End
End
End
ELSE begin
R_WEIGHTONWEIGHTS0A[TEXEL_CNT_Y_R2][TEXEL_CNT_X_R2] <= W_weightonweights0;
End
End

1. The index number of the array must therefore be a constant. If the TEXEL_CNT_Y_R2 is not constant, it is unreasonable.

2.Verilog array does not see the waveform in Verdi, so array is recommended to write switch-case to select the index number.

Verilog Array for Synthsis