Verilog array Parameters

Verilog supports defining array parameters so that when the project is large, the code can be more concise when the module is instantiated: see examples

Module Dma_controller # (
Parameter integer c0_max_mig_bl[3:0] = {2048,2048,2048,2048},
Parameter integer c0_app_data_width[3:0] = {64,64,64,64},
Parameter integer c0_dma_wr_data_width[3:0] = {16,16,16,16},
Parameter integer c0_dma_rd_data_width[3:0] = {16,16,16,16},
parameter [1:8*11] c0_read_write[3:0] = {"WRITE only", "bidirection", "Bidirection", "Bidirection"},
Parameter integer c1_max_mig_bl[3:0] = {2048,2048,2048,2048},
Parameter integer c1_app_data_width[3:0] = {128,128,128,128},
Parameter integer c1_dma_wr_data_width[3:0] = {32,32,32,32},
Parameter integer c1_dma_rd_data_width[3:0] = {32,32,32,32},
parameter [1:8*11] c1_read_write[3:0] = {"WRITE only", "bidirection", "Bidirection", "Bidirection"}
) (
Input MAIN_CLK,//I,W:01,MAIN_CLK main system clock: 200MHz
Input Sys_rst,

。。。。。。

）

Genvar gv_dma_i;
Generate
for (gv_dma_i=0;gv_dma_i<=3;gv_dma_i=gv_dma_i+1)
Begin:c0_dma_blk
Dma
#(
. MAX_MIG_BL (C0_max_mig_bl[gv_dma_i]),
. App_data_width (C0_app_data_width[gv_dma_i]),
. Dma_wr_data_width (C0_dma_wr_data_width[gv_dma_i]),
. Dma_rd_data_width (C0_dma_rd_data_width[gv_dma_i]),
. Read_write (c0_read_write[gv_dma_i])//3 option: "WRITE only", "READ only", "Bidirection"
)
INST_C0_DMA (
With MIG (Arbitor) interface
. UI_CLK (C0_dma_ui_clk[gv_dma_i]),//i,w:01,ui interface output clock, 200Mhz
. Ui_clk_sync_rst (C0_dma_ui_clk_sync_rst[gv_dma_i]),//i,w:01, synchronous clock Reset
. Init_calib_complete (C0_dma_init_calib_complete[gv_dma_i]),//i,w:01,phy calibration complete, DMA can send read and write command information before calibration is completed
. App_req (C0_dma_app_req[gv_dma_i]),//o,w:01,mig UI interface use request
. APP_RESP (C0_mig2dma_app_resp[gv_dma_i]),//i,w:01,mig UI interface uses answer
. App_done (C0_dma2mig_app_done[gv_dma_i]),//o,w:01,mig UI interface end of use, data removal complete
. APP_ADDR (C0_dma2mig_app_addr[gv_dma_i]),//o,w:28or27, current operation address information, first controller address bit width 28, second 27
. App_cmd (C0_dma2mig_app_cmd[gv_dma_i]),//o,w:03, Operation command Read 001,write 000
. App_en (C0_dma2mig_app_en[gv_dma_i]),//O,W:01, command parameter enable, UI interface to capture app_addr[] and app_cmd[2:0 when the signal is valid)
. App_wdf_data (C0_dma2mig_app_wdf_data[gv_dma_i]),//o,w:app_data_width, write data port, bit width depending on MiG controller, when connecting Controller1 With a bit width of 128bit and a bit width of 64bit when connecting to another controller
. App_wdf_end (C0_dma2mig_app_wdf_end[gv_dma_i]),//o,w:01, indicating the current clock cycle app_wdf_data the data on the bus as the last data for this write request
. App_wdf_mask (C0_dma2mig_app_wdf_mask[gv_dma_i]),//O,W:APP_DATA_WIDTH/8, data shielding bit, bit width depending on MiG controller, When the Controller1 is connected, the bit width is 16bit and the other controller is connected with a bit width of 8bit
. App_wdf_wren (C0_dma2mig_app_wdf_wren[gv_dma_i]),//o,w:01, write enable, indicates that the data on the App_wdf_data bus is valid
. App_rd_data (C0_mig2dma_app_rd_data[gv_dma_i]),//i,w:app_data_width, read data port, bit width depending on MiG controller, when connecting Controller1, A bit width of 128bit, a bit width of 64bit when connecting another controller
. App_rd_data_end (C0_mig2dma_app_rd_data_end[gv_dma_i]),//i,w:01, indicating the current clock cycle app_rd_data the data on the bus as the last data for this read request
. App_rd_data_valid (C0_mig2dma_app_rd_data_valid[gv_dma_i]),//i,w:01, read valid, indicating that the data on the App_rd_data bus is valid
. App_rdy (C0_mig2dma_app_rdy[gv_dma_i]),//i,w:01, indicates whether the UI interface has received an operation request just sent, when App_en is valid, if the UI interface does not enable App_rdy, indicating that the operation request was not valid, Need to start a new read and write request
. App_wdf_rdy (C0_mig2dma_app_wdf_rdy[gv_dma_i]),//i,w:01, indicates that the write FIFO is ready to accept data, and the data is written to the FIFO when both App_wdf_rdy and App_wdf_wren are valid

Genvar Gv_dma_j;
Generate
for (gv_dma_j=0;gv_dma_j<=2;gv_dma_j=gv_dma_j+1)
Begin:c1_dma_blk
Dma
#(
. MAX_MIG_BL (C1_max_mig_bl[gv_dma_j]),
. App_data_width (C1_app_data_width[gv_dma_j]),
. Dma_wr_data_width (C1_dma_wr_data_width[gv_dma_j]),
. Dma_rd_data_width (C1_dma_rd_data_width[gv_dma_j]),
. Read_write (C1_read_write[gv_dma_j])//3 option: "WRITE only", "READ only", "Bidirection"
)
INST_C1_DMA (
With MIG (Arbitor) interface
. UI_CLK (C1_dma_ui_clk[gv_dma_j]),//i,w:01,ui interface output clock, 200Mhz
. Ui_clk_sync_rst (C1_dma_ui_clk_sync_rst[gv_dma_j]),//i,w:01, synchronous clock Reset
. Init_calib_complete (C1_dma_init_calib_complete[gv_dma_j]),//i,w:01,phy calibration complete, DMA can send read and write command information before calibration is completed
. App_req (C1_dma_app_req[gv_dma_j]),//o,w:01,mig UI interface use request
. APP_RESP (C1_mig2dma_app_resp[gv_dma_j]),//i,w:01,mig UI interface uses answer
. App_done (C1_dma2mig_app_done[gv_dma_j]),//o,w:01,

Verilog array Parameters