Verilog HDL Notes

Module Module Introduction

• The module is the basic unit of the Verilog HDL language, and the digital system is described in the form of a module.

• A module is an external port that describes the functionality, structure, and communication of other modules of a design.
  

• Each module in the Verilog HDL is run in parallel

• Modules can invoke instances of other modules

Module structure

module <模块名>(<端口列表>)    端口说明（input，output，inout）    参数定义（可选）    数据类型定义//wire、reg、task、function    连续赋值语句（assign）//组合逻辑    过程块（always和initial）    -行为描述语句    低层模块实例//调用其它模块    任务和函数    延时说明块endmodule

Statement Module Description Mode

There are three ways to model Verilog, namely

• Structured description mode

• How data flow is described

• Behavior Description Mode

Structural type description

Using the method described by the example, the pre-defined primitive instance is embedded in the language, the input of the monitoring instance is changed and the operation is re-calculated and output.

Data Flow Type description

is a method of describing the function of combinatorial logic, which is assign implemented by successive assignment statements.

A continuous assignment statement accomplishes the following combination of functions: all variables on the right side of the equation are monitored continuously, and whenever any one of these variables changes, the entire expression is re-assigned and sent to the left side of the equation.

Behavioral-level description

is achieved by describing the behavior characteristics, the key word is always that the meaning of a single sensitive variable can be changed when the issue, the re-assignment, there is an infinite loop meaning. This description method is commonly used to implement sequential circuits, and can also be used to describe combinatorial functions.

Tip

Users can mix the above three description methods, but it is necessary to note that the module's instance of the door, the module instance statement, the Assign statement and the always statement are executed concurrently, that is, the execution order is independent of the writing order.

• Verilog HDL Case-sensitive

• Verilog HDL keywords are generally lowercase

Where the data flow description often uses continuous assignment statements, a value is assigned to a network cable variable.

assign [delay] net_name = expression;

Note that between the Assign statements, execution is performed in parallel, that is, the execution of each statement is independent of the order of the statements.

The behavior description method often uses always, initial statements to assign values. Use reg to register the declaration. Always refers to the repetition of running, triggered by changes in the variable of the ever-trailing parenthesis. Between always and end is executed in serial order.

The Data flow type description is a method to describe the function of combinational logic, which is realized by assign continuous assignment statement.

Constant number

Grammar:

<位宽>‘<进制><数值>

Where bit width refers to the number of digits corresponding to the binary

It is important to note that when the tail is less than the actual number of digits of the corresponding number, the corresponding high part is ignored. 4‘D61with the 4‘B1101 same. Because in decimal 61==111101 , the binary 4bit is required here, so it is 1101 .

Parameter

Grammar:

parameter 参数名1=表达式，参数名2=表达式，......；例：parameter count_bits=8;parameter sel=8,code=8‘ha3;parameter datawidth=8;addwidth=datawidth*2;

Purpose of using constants:

• Easy to read

• Easy to modify

Variable

• Network type Nets type

Refers to the various connections in a hardware circuit, and the output always updates its value according to the input changes.

• Register-type Register type

Commonly referred to in the hardware circuit in the presence of state-preserving devices, such as triggers, registers and so on.

The most important of nets type is the wire type variable, which is commonly used to represent a combined logical signal assigned with a assign statement. Can be a value of 0,1,x (indeterminate), Z (High impedance)

Note that the input and output signal types in the Verilog HDL module are automatically defined as wire-type variables when they are default.

Grammar:
Wire data 1, data 2, ... Data N.

Example:

wire//定义了三个wire型变量wire[7:0//定义了8bit宽wire型向量数据总线wire[20:1] addrbus  //定义了20bit宽的wire型向量地址总线

The reg type in register type is recorded here, and the common register variable

Syntax: REG data 1, data 2, data 3 ...;

Example:

a,b;reg[8:1]//定义可8bit宽的reg型向量reg[7:0] mymem[1023:0]//定义了1024字节（8bit*1024）的存储器

Common statements

• Assignment continuous assignment statement, procedure assignment statement

• Conditional Statement IF-ELSE statement, Case statement

• Looping statements forever, repeat, while, for statements

• Structure Description Statement Initial, always, task, function statement

• Compiling pre-processing statements ' Define ' include ' timescale statements

Process block

1. Always process block

Template:

always @(<敏感信号表达式>)begin    //过程赋值    //if语句      //case语句    //while、repeat、for语句    //task、function调用end

When the value of a sensitive signal expression changes, it executes the inside of the block statement. At the same time, always process blocks can not be nested use.

Key Words posedge And the negedge keywords are rising edge and falling edge, respectively

For example: the clock signal of the synchronous timing circuit is clk,clear for asynchronous clear 0 signal. Sensitive signals can be written as:

//上升沿触发，高电平清0有效@(clear)//上升沿触发，低电平清0有效@(clear)

For example negedge clear , when clear==0 you indicate when

or negedge clear)    begin        if(!clear)//当clear==0时候，always会由事件驱动            qout=0;        else            qout=in;    end

1. Initial process block

Initial templates:

initialbegin    语句1；    语句2；    ......end

Initialization of variables and memory

initialbegin    reg1=0;    for(addr=0;addr<size;addr=addr+1)        memory[addr]=0;end

• Initial statements are primarily for functional simulations and are generally not comprehensive.

• Simulation 0 time to start execution, only once

• Multiple initial process blocks within the same module, simulating 0 time to start parallel execution.

Initial, like the always statement, cannot be nested. That is, the initial statement block cannot be nested again in the initial statement.

Assignment statements

1. Continuous assignment statement Assign is often used to assign values to wire type variables

a,b;output c;assign c=a&b;

Any changes to the B signal will be reflected in C at any time.

1. Procedure assignment Statements are often used to assign values to a reg type variable

Generally there are two ways:

• Non-blocking assignment: The execution of a non-blocking assignment statement does not block the execution of the next statement, which means that the next statement can begin execution until the execution of the non-blocking assignment statement is completed. The non-blocking assignment statement completes the assignment at the end of the block and executes in parallel in a non-blocking assignment statement. Assignment symbols<=

• Block assignment: The completion of the assignment operation at the end of the statement, the preceding statement is not completed, the following statements are not executed, within a block of non-blocking assignment statements executed sequentially. Assignment symbols=

Non-blocking assignment:

module non_block (c, a,b,clk);output c,b;input a,clk;reg c,b;always @(posedge clk)    begin        b<=a;        c<=b;    endendmodule

Due to the non-blocking assignment, BC changes state at the same time as the CLK rising edge. So the b<=a;c<=b; statement executes at the same time, so the value of C is the value of the rising edge of B, and the value of B is assigned the value of the last rising edge of a.

Blocking assignment:

module block (c, a,b,clk);output c,b;input a,clk;reg c,b;always @(posedge clk)    begin        b=a;        c=b;    endendmodule

Sequential execution hasc==b

Conditional statements

If-else statement block

pass

Case statement

case （<敏感表达式>）    值1：语句或语句块1 ；//case分支项    值2：语句或语句块2 ；    ……    值n：语句或语句块n ；    default：语句或语句块n+1；//可省略endcase

Tips

• If all the conditional branches are not listed, the compiler will introduce a trigger to hold the original value when it considers that the condition is not satisfied.

• The timing circuitry can take advantage of the above characteristics to maintain state.

• The combined circuit must list all the conditional branches, otherwise an implicit trigger will be generated.

8bit binary Multiplier integer

 module mult_for (outcome,a,b);Parameter size=8; output[2*Size:1] Outcome;input[Size:1] A, B;//Multiplier reg[2*Size:1] outcome;//Product integer I;always @ (AorbbeginOutcome=0; for(i=1; i<=size;i=i+1)if(B[i]) outcome=outcome+ (a<< (i-1) ) ;EndEndmodule

Task, Functiontask

Define the format:

task<任务名>    端口与类型说明    局部变量说明    语句或语句块endtask

Call Format:

<任务名>(port1，port2，port3,......)

Functional function

Define the format:

function <返回值位宽或类型> <函数名>    输入端口与类型说明    局部变量说明    语句或语句块endfunction

Call Format:

<函数名> (<输入表达式1>,<输入表达式2>,<输入表达式3>,......)

Module Function_example (i, out); input[7:0]inch; output[2:0] out; reg[2:0] out;function[2:0] Gefun; input[7:0] x; Input Port Description reg[2:0] Count;integerIbeginCount=0; for(i=0; i<=7; i=i+1)if(x[i]==1' B0) count=count+1; Gefun=count;EndEndfunction always @ (inch) out=gefun (inch)///Note hereinchTo be the same as the X-bit width endmodule

In the Verilog function declaration, the last sentence of the declaration is usually assigned to the result. That is, assigning a value to the function name. As in the above example, the function name Gefun, the last sentence in the declaration is the assignment of the Gefun.

Compilation preprocessing

• ' Define

• ' Include

• ' Timescale

The compilation instruction begins with a "'" backslash. Unlike single quotes with integers, precompilation uses anti-quotes, typically in the upper-left corner of the keyboard.

Sequential vs. parallel

• Assign statement 之间 : Parallel execution (simultaneous execution)

• Process Block 之间 (always, initial): Parallel execution

• Assign statement and procedure block 之间 : Parallel execution

• Process block (initial, always) interior

  1. Serial Block (begin-end): Sequential execution-non-blocking statements similar to parallel statements

  2. Parallel Fast (Fork-join): Parallel execution

Verilog HDL Notes