Verilog (ii)

Display tasks: $display, $write, the former always outputs a newline character, which does not. Fixed output format version: $displayb/$displayo/$displayh/$WRITEB/$writeo/$writeh.

(%m display module path, \ Escape character) $fmonitor (file, "%m:%t addr =%h data =%h", $realtime, addr, data);

Monitoring task: $monitor, $strobe, the former can only trigger a task when the same simulation, there are control tasks $monitoron, $monitoroff. The latter, at some point, records the value of the variable to log and stdout, at which time all the event has been triggered and the simulation times will go forward. Forever @ (Negedge clock) $strobe ("At time%t, data is%h", $time, data);

File read and write: $fopen, $fclose handle must be a interger type. Type r/w/a (append), default is write when r+/w+/a+ defaults.

Interger Write_out_file;  Write_out_file = $fopen ("Write_out_file.txt");  $fdisplay (Write_out_file, "%h\n%h", addr, data); $fclose (Write_out_file);

$fdisplay, $fwrite, $fstrobe, $fmonitor usage is similar, you only need to add a file handle. Similar to $fwriteo, $fwriteb, $fwriteh and so on.

A few other special tasks:

c = $fgetc (FD); Read a byte to C.

$swrite, $sformat (Output_reg, formal_string, list_of_argument) output to a reg variable in string format.

$fgets (str, FD), read a line of characters into Str.

$FSCANF (FD, format, args); Input to file FD as standard.

$SSCANF (str, format, args), by standard input to Reg str.

$fflush (FD); The buffer is immediately output to the FD file.

Write Memory: $readmemb/READMEMH binary with 16 binary.  REG[7:0] mem[1:256]; Initial $READMEMH ("Mem_data", Mem, 128, 1);

(Mem_data can only have spaces, tabs, etc., comments, 2 binary/16 binary data.) Third start address, fourth end address, not specified, default from 0--$)

$sdf _annotate ("Sdf_file",,,,,,): Read the SDF file into the design. Optional Parameters module_instance (inverse module, default current modules), Log_file (Specify the name of the output log), Mtm_spec (Min/typ/max inverse category), Scale_factor (scale factor), Scale_type (Scale is selected in Min/typ/max).

Simulation control: $finish, $stop

Random number generation: $random (Seed), $dist _uniform (seed, start, end); Returns a random number with a signed 32-bit.

Command line Input: $test $plusargs (String)

Run simulator with +hello initial begin

if ($test $pluargs ("HELLO")) $display ();

End

$value $pluargs (user_string, variable)

Run Simulator with +testname = this TEST initial begin

                                                                                        if ($value $pluargs ("testname =%s", testname)    start_test ();         

End

Verilog (ii)