Formula for propagation delay of cabling in PCB

Formula for propagation delay of cabling in PCB

The first half is information from altera.

The propagation latency (tPD) is the time required to transmit a signal from one point to another. Transmission Line propagation delay is a function of the relative dielectric constant of materials.

Propagation delay of micro-Strip Layout

You can use formula 5 to calculate the propagation delay of the strip layout.

Formula 5:

Delayed propagation in the line layout

You can use formula 6 to calculate the propagation latency of the linear layout.

Formula 6:

Figure 9 shows the relationship between the propagation delay and relative dielectric constant of the microline and the strip. As ε r increases, the propagation latency (tPD) also increases.

Figure 9. Relationship between transmission delay and relative dielectric constant of the microline and the strip

F = 0.5/Tr

Tr is the time when the signal rises. It generally refers to the time when the signal rises from 10% to 90% or from 20% to 80%. Whether a high-frequency circuit depends on the signal rising/falling edge rather than the clock frequency.

F2 = 1/(Tr × π)> 100 M, system clock> 50 M, devices with a rise/fall time less than 5ns, or digital-analog hybrid circuits should be designed based on high-frequency circuits.

In addition, there is another question that was not answered correctly before:

The latency Tpd produced by cabling per inch of the PCB can be estimated at 0.167ns, that is, about 2cm brings 1ns latency. Tr> 4 Tpd can ensure that the signal falls into the secure zone.

The distribution parameters, media and any other parameters are not discussed in the document. This is only a reference for future interviews or written tests. In addition, the jellyfish serum area also says "30cm brings 2ns latency.

PS: copy an estimation method for reference. Let's discuss the correctness:

The width of the microline is 10mil, the copper-coated thickness is 1mil, the Board spacing is 30mil, and the medium ε is 5 (FR4 seems to be about 4.5)

Tpd = 1.017 × Power (0.456 × ε + 0.67), 0.5) ns/ft

= 1.747 ns/ft

I suddenly found that we were actually calculating some of the microline-related parameters.

Two commonly referenced characteristic impedance formulas:

A. microstrip)

Z = {87/[sqrt (Er + 1.41)]} ln [5.98 H/(0.8 W + T)] where W is the line width, T is the copper thickness of the wire, H is the distance from the wire to the reference plane. Er is the dielectric constant (dielectric constant) of the PCB ). This formula can be used only when 0.1 <(W/H) <2.0 and 1 <(Er) <15.

B. stripline)

Z = [60/sqrt (Er)] ln {4 H/[0.67 π (T + 0.8 W)]} Where H is the distance between the two reference planes, and the cabling is located in the middle of the two reference planes. This formula can be used only when W/H <0.35 and T/H <0.25.

Generally, if the frequency of a digital logic circuit reaches or exceeds 45 MHz ~ 50 MHZ, and the circuit working above this frequency has occupied a certain part of the entire electronic system (for example, 1/3), is called a high-speed circuit.

In fact, the harmonic frequency at the signal edge is higher than the frequency of the signal itself, which is the unexpected result of signal transmission due to the rising and falling sides of the rapid signal change (or the hop of the signal. Therefore, it is generally agreed that if the linear transmission delay is greater than 1/2 of the rising time of the digital signal driving end, such signals are considered as high-speed signals and produce Transmission Line effects.

Signal Transmission occurs when the signal status changes, such as the time when the signal is increased or decreased. The signal goes through a fixed period of time from the driver end to the receiver end. If the transmission time is less than 1/2 of the increase or decrease time, the reflection signal from the receiver will arrive at the driver end before the signal changes. Otherwise, the reflected signal will arrive at the driver end after the signal changes. If the reflected signal is strong, the superimposed waveform may change the logical state.

We have defined the precondition for the occurrence of Transmission Line effects, but how can we determine whether the signal rise time of the transmission line delay is greater than 1/2? Generally, the typical value of the signal rise time can be provided through the device manual, and the signal propagation time is determined by the actual wiring length in the PCB design. It is the correspondence between the signal rise time and the allowable wiring length (Delay.

The latency per inch on the PCB Board is 0.167ns .. However, if there are too many holes and many device pins, and there are many constraints set on the network cable, the latency will increase. Generally, the signal rise time of a high-speed logical device is about 0.2ns. The maximum wiring length is 7.62mm if the receiving board has a AAS chip. Set Tr to the signal rising time, and Tpd to the signal transmission delay. If Tr is greater than or equal to 4Tpd, the signal falls into the safe area. If 2Tpd is greater than or equal to Tr or greater than 4Tpd, the signal falls into the uncertain area. If Tr ≤ 2Tpd, the signal falls into the problem area. The high-speed cabling method should be used for signals falling in uncertain regions and problem areas.

Based on the above introduction, the tester calculated the wiring requirements and the Equi-length calculation. We can see that the gap error of the line length is less than mil. 2410 Tr = 0.2ns [1/500 MHz] Tpd = 1/4 * Tr = 0.05ns Allowed signal line differences: 0.05ns/(0.167ns/inches) = 0.2994 inch = 299.4mil = 7.5mm.