Fourth Chapter processor Architecture

Fourth processor architecture first section Y86 instruction set architecture Y86 directives

IA32 's MOVL directive is divided into four types:irmovl,rrmovl,mrmovl,rmmovl

Unlike the Ia332, the limit bit, IM, the front letter means the money an operand is passed to the abbreviation of an operand

※ The memory reference method here is a simple base address and offset form, and the addressing method does not support the scaling of the second variable address register and any register value.

※ Two operands cannot be from the memory, nor allow the immediate number to be transmitted to the memory.

Four integer operation instructions

addl 加subl 减andl 与xorl 异或

These instructions will set up three condition codes :

ZF-零 SF-符号OF-溢出

Seven Jump commands--branch control

jmp 直接跳转jle（SF^OF）|ZF 有符号数≤jl SF^OF 有符号＜je ZF 相等/零jne ~ZF 不相等/非零jge ~(SF^OF) 有符号≥jg ~(SF^OF)&~ZF 有符号＞

Six conditional delivery Instructions

cmovlecmovlcmovecmovnecmovgecmovg

The format of these instructions is the same as the Register-register transfer Directive , but the value of the destination register is updated only if the condition code satisfies the required constraint RRMOVL.

Call and RET

The call instruction returns the address to the stack, and then jumps to the destination address, which is returned from such a procedure invocation.

PUSHL and POPL

Implement in-stack and out-stack

Halt directive

The halt instruction stops the execution of the instruction, which causes the processor to stop and the status code to be set to HLT.

The analogy ia32:hlt directive is similar, but the IA32 application does not allow this instruction because it causes the entire system to pause.

Precautions:

1, unlike IA, is the wording of some instructions

2, the logical function and other operations need to be different from the function, and there is no large operation like IA, the operation of other functions required by the basic operation of composite

byte-level encoding of the instruction

Each instruction requires a range of 1-6 bytes, and the first byte of each instruction indicates the type of instruction .

This byte is divided into two parts

• High four-bit: Code section, domain value is 0~0xb
• Fourth bit: Functional part, function value is only useful if a set of related instructions is shared with one code.

Precautions:

1 When you need to indicate that no registers should be accessed, use the ID value 0xF to indicate

2 write sequences are compiled in small notation

3 Usually, the former sequence is the operation instruction, the back is the corresponding operation address, and the absolute address

Y86 exception 1. Possible value of status code stat

Stat describes the overall state of the program execution

1. AOK 正常操作2. HLT 处理器执行halt指令3. ADR 遇到非法地址4. INS 遇到非法指令

When an exception occurs, the y86--processor stops running instructions.

Precautions:

1 These instructions need to determine the status code

2 can be easily interrupted operation, such as Call 21H

Summary:

Y86 language is closer to the machine, many operations can be replaced with basic operations, will be re-written as a simple operation of the combination

Y86 does not have the corresponding recognition ability, only the corresponding sequence to do the corresponding operation, mainly reflected in the same statement pop PUSHL will appear ambiguous

Section II Logic Design and hardware control Language HCL logic gate AND && ，OR || ，NOT !

HCL: Logical expressions are logical relationships

Summary:

is to correspond to the logical relation, write out the correspondence relation

Similar to the machine practice

Sequential implementation of Y86

SEQ Processor

First, the process of organizing into phase (i) six basic stages:

• Take a finger
• Decoding
• Perform
• Visit
• Write back
• Update pc

Summary:

The main focus on the different instructions need to correspond to different stages, mainly the combination of the stages

Seq is a bit like the programming of routers, when it is necessary to process the information will be added to the corresponding address to operate and return the results back

Renewal facilitates long-term use of the system

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Fourth Chapter processor Architecture