FPGA-driven SDRAM control compatibility transplant experiment

CB early in 2012 on the introduction of the VIP Video Development Board V1.4 This set of development Board is EP2, the camera is ov7670, although not as powerful as the current VIP20, but also the embryonic form.

In the late VIP20, the CB was encapsulated with SDRAM and other modules, making it more reliable and more stable.

Obviously, SDRAM to be more stable, more reliable, verification, need to carry out a lot of experiments, using a variety of ICS, but experienced CB, but also have missed test (PS: Note on a blog details)

So find vip1.4 05_sdram_vga_test routines, sure enough, this routine compatibility is very good, vip2.0 can not use the program to use this is OK.

Okay, now I need to re-port the 1.4 program to 2.0 to verify compatibility.

First look at the interface

Rtl

Read above interface

In contrast to the mainstream structure of VIP2.0

The changes are as follows: for vip1.4

1, Sdram_vga_top split into VGA and SDRAM placed on the top floor

2, sdram_vga_top internal removal of Sdbank_switch module, because the association too many signals, remove this module is to streamline, simplify, temporarily do not need ping-pong and other functions.

3, SDRAM interface processing

. WR_ADDR ({D0}),//sdram start write address
. WR_MAX_ADDR ({d786432}),//sdram Max write address
. Wr_load (wr_load),//sdram write address reset
. RD_ADDR ({D0}),//sdram start read address
. RD_MAX_ADDR ({d786432}),//sdram Max Read address
. Rd_load (0),//sdram read address reset

4. Increase the trigger signal

Reg F1;
Reg F2;
Reg F3;
Reg F4;
Reg F5;
[Email protected] (Posedge clk_write)
Begin
f1<=frame_valid;
f2<=f1;
f3<=f2;
f4<=f3;
f5<=f4;
End
Wire Wr_load=pos_edge;
Wire Neg_edge =! F1 & F2;
Wire Pos_edge = F1 &! F2;

The test has been completed since.

FPGA-driven SDRAM control compatibility transplant experiment